602610383f
Introduce an AspeedI2CBus SysBusDevice model and attach the associated memory region and IRQ to the newly instantiated objects. Before this change, the I2C bus IRQs were all attached to the SysBusDevice model of the I2C controller. Adapt the AST2600 SoC realize routine to take into account this change. Signed-off-by: Cédric Le Goater <clg@kaod.org>
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
/*
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* ASPEED AST2400 I2C Controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef ASPEED_I2C_H
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#define ASPEED_I2C_H
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#include "hw/i2c/i2c.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_ASPEED_I2C "aspeed.i2c"
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#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
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#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
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#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
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OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
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#define ASPEED_I2C_NR_BUSSES 16
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#define ASPEED_I2C_MAX_POOL_SIZE 0x800
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struct AspeedI2CState;
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#define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus"
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS)
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struct AspeedI2CBus {
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SysBusDevice parent_obj;
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struct AspeedI2CState *controller;
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MemoryRegion mr;
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I2CBus *bus;
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uint8_t id;
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qemu_irq irq;
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uint32_t ctrl;
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uint32_t timing[2];
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uint32_t intr_ctrl;
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uint32_t intr_status;
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uint32_t cmd;
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uint32_t buf;
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uint32_t pool_ctrl;
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uint32_t dma_addr;
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uint32_t dma_len;
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};
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struct AspeedI2CState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t intr_status;
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uint32_t ctrl_global;
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MemoryRegion pool_iomem;
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uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
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AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
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MemoryRegion *dram_mr;
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AddressSpace dram_as;
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};
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struct AspeedI2CClass {
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SysBusDeviceClass parent_class;
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uint8_t num_busses;
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uint8_t reg_size;
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uint8_t gap;
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qemu_irq (*bus_get_irq)(AspeedI2CBus *);
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uint64_t pool_size;
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hwaddr pool_base;
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uint8_t *(*bus_pool_base)(AspeedI2CBus *);
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bool check_sram;
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bool has_dma;
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};
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I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
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#endif /* ASPEED_I2C_H */
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