The AArch32 DBGDIDR defines properties like the number of breakpoints, watchpoints and context-matching comparators. On an AArch64 CPU, the register may not even exist if AArch32 is not supported at EL1. Currently we hard-code use of DBGDIDR to identify the number of breakpoints etc; this works for all our TCG CPUs, but will break if we ever add an AArch64-only CPU. We also have an assert() that the AArch32 and AArch64 registers match, which currently works only by luck for KVM because we don't populate either of these ID registers from the KVM vCPU and so they are both zero. Clean this up so we have functions for finding the number of breakpoints, watchpoints and context comparators which look in the appropriate ID register. This allows us to drop the "check that AArch64 and AArch32 agree on the number of breakpoints etc" asserts: * we no longer look at the AArch32 versions unless that's the right place to be looking * it's valid to have a CPU (eg AArch64-only) where they don't match * we shouldn't have been asserting the validity of ID registers in a codepath used with KVM anyway Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200214175116.9164-11-peter.maydell@linaro.org
338 lines
9.5 KiB
C
338 lines
9.5 KiB
C
/*
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* ARM debug helpers.
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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/* Return true if the linked breakpoint entry lbn passes its checks */
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static bool linked_bp_matches(ARMCPU *cpu, int lbn)
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{
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CPUARMState *env = &cpu->env;
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uint64_t bcr = env->cp15.dbgbcr[lbn];
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int brps = arm_num_brps(cpu);
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int ctx_cmps = arm_num_ctx_cmps(cpu);
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int bt;
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uint32_t contextidr;
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uint64_t hcr_el2;
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/*
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* Links to unimplemented or non-context aware breakpoints are
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* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
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* as if linked to an UNKNOWN context-aware breakpoint (in which
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* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
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* We choose the former.
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*/
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if (lbn >= brps || lbn < (brps - ctx_cmps)) {
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return false;
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}
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bcr = env->cp15.dbgbcr[lbn];
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if (extract64(bcr, 0, 1) == 0) {
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/* Linked breakpoint disabled : generate no events */
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return false;
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}
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bt = extract64(bcr, 20, 4);
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hcr_el2 = arm_hcr_el2_eff(env);
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switch (bt) {
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case 3: /* linked context ID match */
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switch (arm_current_el(env)) {
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default:
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/* Context matches never fire in AArch64 EL3 */
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return false;
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case 2:
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if (!(hcr_el2 & HCR_E2H)) {
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/* Context matches never fire in EL2 without E2H enabled. */
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return false;
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}
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contextidr = env->cp15.contextidr_el[2];
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break;
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case 1:
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contextidr = env->cp15.contextidr_el[1];
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break;
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case 0:
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if ((hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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contextidr = env->cp15.contextidr_el[2];
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} else {
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contextidr = env->cp15.contextidr_el[1];
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}
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break;
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}
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break;
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case 7: /* linked contextidr_el1 match */
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contextidr = env->cp15.contextidr_el[1];
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break;
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case 13: /* linked contextidr_el2 match */
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contextidr = env->cp15.contextidr_el[2];
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break;
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case 9: /* linked VMID match (reserved if no EL2) */
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case 11: /* linked context ID and VMID match (reserved if no EL2) */
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case 15: /* linked full context ID match */
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default:
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/*
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* Links to Unlinked context breakpoints must generate no
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* events; we choose to do the same for reserved values too.
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*/
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return false;
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}
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/*
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* We match the whole register even if this is AArch32 using the
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* short descriptor format (in which case it holds both PROCID and ASID),
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* since we don't implement the optional v7 context ID masking.
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*/
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return contextidr == (uint32_t)env->cp15.dbgbvr[lbn];
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}
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static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
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{
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CPUARMState *env = &cpu->env;
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uint64_t cr;
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int pac, hmc, ssc, wt, lbn;
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/*
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* Note that for watchpoints the check is against the CPU security
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* state, not the S/NS attribute on the offending data access.
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*/
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bool is_secure = arm_is_secure(env);
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int access_el = arm_current_el(env);
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if (is_wp) {
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CPUWatchpoint *wp = env->cpu_watchpoint[n];
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if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
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return false;
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}
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cr = env->cp15.dbgwcr[n];
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if (wp->hitattrs.user) {
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/*
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* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
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* match watchpoints as if they were accesses done at EL0, even if
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* the CPU is at EL1 or higher.
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*/
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access_el = 0;
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}
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} else {
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uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
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if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
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return false;
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}
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cr = env->cp15.dbgbcr[n];
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}
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/*
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* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
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* enabled and that the address and access type match; for breakpoints
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* we know the address matched; check the remaining fields, including
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* linked breakpoints. We rely on WCR and BCR having the same layout
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* for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
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* Note that some combinations of {PAC, HMC, SSC} are reserved and
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* must act either like some valid combination or as if the watchpoint
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* were disabled. We choose the former, and use this together with
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* the fact that EL3 must always be Secure and EL2 must always be
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* Non-Secure to simplify the code slightly compared to the full
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* table in the ARM ARM.
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*/
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pac = extract64(cr, 1, 2);
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hmc = extract64(cr, 13, 1);
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ssc = extract64(cr, 14, 2);
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switch (ssc) {
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case 0:
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break;
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case 1:
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case 3:
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if (is_secure) {
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return false;
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}
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break;
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case 2:
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if (!is_secure) {
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return false;
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}
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break;
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}
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switch (access_el) {
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case 3:
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case 2:
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if (!hmc) {
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return false;
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}
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break;
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case 1:
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if (extract32(pac, 0, 1) == 0) {
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return false;
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}
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break;
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case 0:
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if (extract32(pac, 1, 1) == 0) {
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return false;
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}
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break;
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default:
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g_assert_not_reached();
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}
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wt = extract64(cr, 20, 1);
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lbn = extract64(cr, 16, 4);
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if (wt && !linked_bp_matches(cpu, lbn)) {
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return false;
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}
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return true;
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}
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static bool check_watchpoints(ARMCPU *cpu)
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{
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CPUARMState *env = &cpu->env;
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int n;
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/*
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* If watchpoints are disabled globally or we can't take debug
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* exceptions here then watchpoint firings are ignored.
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*/
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if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
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|| !arm_generate_debug_exceptions(env)) {
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return false;
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}
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for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
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if (bp_wp_matches(cpu, n, true)) {
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return true;
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}
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}
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return false;
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}
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static bool check_breakpoints(ARMCPU *cpu)
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{
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CPUARMState *env = &cpu->env;
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int n;
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/*
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* If breakpoints are disabled globally or we can't take debug
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* exceptions here then breakpoint firings are ignored.
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*/
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if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
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|| !arm_generate_debug_exceptions(env)) {
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return false;
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}
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for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
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if (bp_wp_matches(cpu, n, false)) {
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return true;
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}
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}
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return false;
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}
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void HELPER(check_breakpoints)(CPUARMState *env)
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{
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ARMCPU *cpu = env_archcpu(env);
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if (check_breakpoints(cpu)) {
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HELPER(exception_internal(env, EXCP_DEBUG));
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}
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}
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bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
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{
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/*
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* Called by core code when a CPU watchpoint fires; need to check if this
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* is also an architectural watchpoint match.
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*/
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ARMCPU *cpu = ARM_CPU(cs);
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return check_watchpoints(cpu);
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}
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void arm_debug_excp_handler(CPUState *cs)
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{
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/*
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* Called by core code when a watchpoint or breakpoint fires;
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* need to check which one and raise the appropriate exception.
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*/
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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CPUWatchpoint *wp_hit = cs->watchpoint_hit;
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if (wp_hit) {
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if (wp_hit->flags & BP_CPU) {
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bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
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bool same_el = arm_debug_target_el(env) == arm_current_el(env);
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cs->watchpoint_hit = NULL;
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env->exception.fsr = arm_debug_exception_fsr(env);
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env->exception.vaddress = wp_hit->hitaddr;
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raise_exception(env, EXCP_DATA_ABORT,
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syn_watchpoint(same_el, 0, wnr),
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arm_debug_target_el(env));
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}
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} else {
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uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
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bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
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/*
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* (1) GDB breakpoints should be handled first.
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* (2) Do not raise a CPU exception if no CPU breakpoint has fired,
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* since singlestep is also done by generating a debug internal
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* exception.
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*/
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if (cpu_breakpoint_test(cs, pc, BP_GDB)
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|| !cpu_breakpoint_test(cs, pc, BP_CPU)) {
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return;
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}
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env->exception.fsr = arm_debug_exception_fsr(env);
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/*
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* FAR is UNKNOWN: clear vaddress to avoid potentially exposing
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* values to the guest that it shouldn't be able to see at its
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* exception/security level.
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*/
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env->exception.vaddress = 0;
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raise_exception(env, EXCP_PREFETCH_ABORT,
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syn_breakpoint(same_el),
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arm_debug_target_el(env));
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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/*
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* In BE32 system mode, target memory is stored byteswapped (on a
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* little-endian host system), and by the time we reach here (via an
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* opcode helper) the addresses of subword accesses have been adjusted
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* to account for that, which means that watchpoints will not match.
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* Undo the adjustment here.
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*/
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if (arm_sctlr_b(env)) {
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if (len == 1) {
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addr ^= 3;
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} else if (len == 2) {
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addr ^= 2;
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}
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}
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return addr;
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}
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#endif
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