Currently creating a memory region automatically registers it for live migration. This differs from other state (which is enumerated in a VMStateDescription structure) and ties the live migration code into the memory core. Decouple the two by introducing a separate API, vmstate_register_ram(), for registering a RAM block for migration. Currently the same implementation is reused, but later it can be moved into a separate list, and registrations can be moved to VMStateDescription blocks. Signed-off-by: Avi Kivity <avi@redhat.com>
1204 lines
33 KiB
C
1204 lines
33 KiB
C
/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "apic.h"
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#include "fdc.h"
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#include "ide.h"
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#include "pci.h"
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#include "vmware_vga.h"
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#include "monitor.h"
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#include "fw_cfg.h"
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#include "hpet_emul.h"
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#include "smbios.h"
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#include "loader.h"
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#include "elf.h"
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#include "multiboot.h"
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#include "mc146818rtc.h"
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#include "msix.h"
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#include "sysbus.h"
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#include "sysemu.h"
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#include "blockdev.h"
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#include "ui/qemu-spice.h"
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#include "memory.h"
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#include "exec-memory.h"
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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/* debug PC/ISA interrupts */
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define BIOS_FILENAME "bios.bin"
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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#define ACPI_DATA_SIZE 0x10000
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#define BIOS_CFG_IOPORT 0x510
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
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#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
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#define MSI_ADDR_BASE 0xfee00000
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#define E820_NR_ENTRIES 16
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struct e820_entry {
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uint64_t address;
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uint64_t length;
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uint32_t type;
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} QEMU_PACKED __attribute((__aligned__(4)));
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struct e820_table {
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uint32_t count;
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struct e820_entry entry[E820_NR_ENTRIES];
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} QEMU_PACKED __attribute((__aligned__(4)));
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static struct e820_table e820_table;
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struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
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void gsi_handler(void *opaque, int n, int level)
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{
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GSIState *s = opaque;
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DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
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if (n < ISA_NUM_IRQS) {
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qemu_set_irq(s->i8259_irq[n], level);
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}
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qemu_set_irq(s->ioapic_irq[n], level);
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}
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
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}
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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void pc_register_ferr_irq(qemu_irq irq)
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{
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ferr_irq = irq;
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}
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{
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qemu_irq_raise(ferr_irq);
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}
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
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{
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qemu_irq_lower(ferr_irq);
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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return cpu_get_ticks();
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}
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/* SMM support */
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static cpu_set_smm_t smm_set;
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static void *smm_arg;
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void cpu_smm_register(cpu_set_smm_t callback, void *arg)
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{
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assert(smm_set == NULL);
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assert(smm_arg == NULL);
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smm_set = callback;
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smm_arg = arg;
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}
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void cpu_smm_update(CPUState *env)
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{
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if (smm_set && smm_arg && env == first_cpu)
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smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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int intno;
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intno = apic_get_interrupt(env->apic_state);
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if (intno >= 0) {
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return intno;
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}
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env->apic_state)) {
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return -1;
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}
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intno = pic_read_irq(isa_pic);
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return intno;
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}
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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CPUState *env = first_cpu;
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DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env->apic_state)) {
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apic_deliver_pic_intr(env->apic_state, level);
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}
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env = env->next_cpu;
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}
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} else {
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14
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static int cmos_get_fd_drive_type(FDriveType fd0)
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{
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int val;
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switch (fd0) {
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case FDRIVE_DRV_144:
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case FDRIVE_DRV_288:
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case FDRIVE_DRV_120:
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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case FDRIVE_DRV_NONE:
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default:
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val = 0;
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break;
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}
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return val;
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}
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
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ISADevice *s)
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{
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int cylinders, heads, sectors;
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bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors);
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders);
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff);
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rtc_set_memory(s, info_ofs + 4, 0xff);
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
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rtc_set_memory(s, info_ofs + 8, sectors);
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}
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device)
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{
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switch(boot_device) {
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case 'a':
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case 'b':
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return 0x01; /* floppy boot */
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case 'c':
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return 0x02; /* hard drive boot */
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case 'd':
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return 0x03; /* CD-ROM boot */
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case 'n':
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return 0x04; /* Network boot */
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}
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return 0;
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}
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static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
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{
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#define PC_MAX_BOOT_DEVICES 3
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int nbds, bds[3] = { 0, };
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int i;
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nbds = strlen(boot_device);
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if (nbds > PC_MAX_BOOT_DEVICES) {
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error_report("Too many boot devices for PC");
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return(1);
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}
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for (i = 0; i < nbds; i++) {
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bds[i] = boot_device2nibble(boot_device[i]);
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if (bds[i] == 0) {
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error_report("Invalid boot device for PC: '%c'",
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boot_device[i]);
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return(1);
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}
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}
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
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rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
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return(0);
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}
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static int pc_boot_set(void *opaque, const char *boot_device)
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{
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return set_boot_dev(opaque, boot_device, 0);
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}
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typedef struct pc_cmos_init_late_arg {
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ISADevice *rtc_state;
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BusState *idebus0, *idebus1;
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} pc_cmos_init_late_arg;
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static void pc_cmos_init_late(void *opaque)
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{
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pc_cmos_init_late_arg *arg = opaque;
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ISADevice *s = arg->rtc_state;
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int val;
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BlockDriverState *hd_table[4];
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int i;
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ide_get_bs(hd_table, arg->idebus0);
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ide_get_bs(hd_table + 2, arg->idebus1);
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rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
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if (hd_table[0])
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cmos_init_hd(0x19, 0x1b, hd_table[0], s);
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if (hd_table[1])
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cmos_init_hd(0x1a, 0x24, hd_table[1], s);
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val = 0;
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for (i = 0; i < 4; i++) {
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if (hd_table[i]) {
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int cylinders, heads, sectors, translation;
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/* NOTE: bdrv_get_geometry_hint() returns the physical
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geometry. It is always such that: 1 <= sects <= 63, 1
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<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
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geometry can be different if a translation is done. */
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translation = bdrv_get_translation_hint(hd_table[i]);
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if (translation == BIOS_ATA_TRANSLATION_AUTO) {
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bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors);
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if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
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/* No translation. */
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translation = 0;
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} else {
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/* LBA translation. */
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translation = 1;
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}
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} else {
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translation--;
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}
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val |= translation << (i * 2);
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}
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}
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rtc_set_memory(s, 0x39, val);
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qemu_unregister_reset(pc_cmos_init_late, opaque);
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}
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void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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const char *boot_device,
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ISADevice *floppy, BusState *idebus0, BusState *idebus1,
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ISADevice *s)
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{
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int val, nb, nb_heads, max_track, last_sect, i;
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FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
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BlockDriverState *fd[MAX_FD];
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static pc_cmos_init_late_arg arg;
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/* various important CMOS locations needed by PC/Bochs bios */
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/* memory size */
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val = 640; /* base memory in K */
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rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8);
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val = (ram_size / 1024) - 1024;
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if (val > 65535)
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val = 65535;
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8);
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rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8);
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if (above_4g_mem_size) {
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rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
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rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
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rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
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}
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if (ram_size > (16 * 1024 * 1024))
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val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
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else
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val = 0;
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if (val > 65535)
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val = 65535;
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rtc_set_memory(s, 0x34, val);
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rtc_set_memory(s, 0x35, val >> 8);
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/* set the number of CPU */
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rtc_set_memory(s, 0x5f, smp_cpus - 1);
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/* set boot devices, and disable floppy signature check if requested */
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if (set_boot_dev(s, boot_device, fd_bootchk)) {
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exit(1);
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}
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/* floppy type */
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if (floppy) {
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fdc_get_bs(fd, floppy);
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for (i = 0; i < 2; i++) {
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if (fd[i] && bdrv_is_inserted(fd[i])) {
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bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
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&last_sect, FDRIVE_DRV_NONE,
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&fd_type[i]);
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}
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}
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}
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val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
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cmos_get_fd_drive_type(fd_type[1]);
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rtc_set_memory(s, 0x10, val);
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val = 0;
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nb = 0;
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if (fd_type[0] < FDRIVE_DRV_NONE) {
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nb++;
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}
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if (fd_type[1] < FDRIVE_DRV_NONE) {
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nb++;
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}
|
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switch (nb) {
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case 0:
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break;
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case 1:
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val |= 0x01; /* 1 drive, ready for boot */
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break;
|
|
case 2:
|
|
val |= 0x41; /* 2 drives, ready for boot */
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break;
|
|
}
|
|
val |= 0x02; /* FPU is there */
|
|
val |= 0x04; /* PS/2 mouse installed */
|
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rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
|
|
|
|
/* hard drives */
|
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arg.rtc_state = s;
|
|
arg.idebus0 = idebus0;
|
|
arg.idebus1 = idebus1;
|
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qemu_register_reset(pc_cmos_init_late, &arg);
|
|
}
|
|
|
|
/* port 92 stuff: could be split off */
|
|
typedef struct Port92State {
|
|
ISADevice dev;
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|
MemoryRegion io;
|
|
uint8_t outport;
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qemu_irq *a20_out;
|
|
} Port92State;
|
|
|
|
static void port92_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
Port92State *s = opaque;
|
|
|
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DPRINTF("port92: write 0x%02x\n", val);
|
|
s->outport = val;
|
|
qemu_set_irq(*s->a20_out, (val >> 1) & 1);
|
|
if (val & 1) {
|
|
qemu_system_reset_request();
|
|
}
|
|
}
|
|
|
|
static uint32_t port92_read(void *opaque, uint32_t addr)
|
|
{
|
|
Port92State *s = opaque;
|
|
uint32_t ret;
|
|
|
|
ret = s->outport;
|
|
DPRINTF("port92: read 0x%02x\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
static void port92_init(ISADevice *dev, qemu_irq *a20_out)
|
|
{
|
|
Port92State *s = DO_UPCAST(Port92State, dev, dev);
|
|
|
|
s->a20_out = a20_out;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_port92_isa = {
|
|
.name = "port92",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.fields = (VMStateField []) {
|
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VMSTATE_UINT8(outport, Port92State),
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VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void port92_reset(DeviceState *d)
|
|
{
|
|
Port92State *s = container_of(d, Port92State, dev.qdev);
|
|
|
|
s->outport &= ~1;
|
|
}
|
|
|
|
static const MemoryRegionPortio port92_portio[] = {
|
|
{ 0, 1, 1, .read = port92_read, .write = port92_write },
|
|
PORTIO_END_OF_LIST(),
|
|
};
|
|
|
|
static const MemoryRegionOps port92_ops = {
|
|
.old_portio = port92_portio
|
|
};
|
|
|
|
static int port92_initfn(ISADevice *dev)
|
|
{
|
|
Port92State *s = DO_UPCAST(Port92State, dev, dev);
|
|
|
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memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
|
|
isa_register_ioport(dev, &s->io, 0x92);
|
|
|
|
s->outport = 0;
|
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return 0;
|
|
}
|
|
|
|
static ISADeviceInfo port92_info = {
|
|
.qdev.name = "port92",
|
|
.qdev.size = sizeof(Port92State),
|
|
.qdev.vmsd = &vmstate_port92_isa,
|
|
.qdev.no_user = 1,
|
|
.qdev.reset = port92_reset,
|
|
.init = port92_initfn,
|
|
};
|
|
|
|
static void port92_register(void)
|
|
{
|
|
isa_qdev_register(&port92_info);
|
|
}
|
|
device_init(port92_register)
|
|
|
|
static void handle_a20_line_change(void *opaque, int irq, int level)
|
|
{
|
|
CPUState *cpu = opaque;
|
|
|
|
/* XXX: send to all CPUs ? */
|
|
/* XXX: add logic to handle multiple A20 line sources */
|
|
cpu_x86_set_a20(cpu, level);
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* Bochs BIOS debug ports */
|
|
|
|
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
static const char shutdown_str[8] = "Shutdown";
|
|
static int shutdown_index = 0;
|
|
|
|
switch(addr) {
|
|
/* Bochs BIOS messages */
|
|
case 0x400:
|
|
case 0x401:
|
|
/* used to be panic, now unused */
|
|
break;
|
|
case 0x402:
|
|
case 0x403:
|
|
#ifdef DEBUG_BIOS
|
|
fprintf(stderr, "%c", val);
|
|
#endif
|
|
break;
|
|
case 0x8900:
|
|
/* same as Bochs power off */
|
|
if (val == shutdown_str[shutdown_index]) {
|
|
shutdown_index++;
|
|
if (shutdown_index == 8) {
|
|
shutdown_index = 0;
|
|
qemu_system_shutdown_request();
|
|
}
|
|
} else {
|
|
shutdown_index = 0;
|
|
}
|
|
break;
|
|
|
|
/* LGPL'ed VGA BIOS messages */
|
|
case 0x501:
|
|
case 0x502:
|
|
exit((val << 1) | 1);
|
|
case 0x500:
|
|
case 0x503:
|
|
#ifdef DEBUG_BIOS
|
|
fprintf(stderr, "%c", val);
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
|
|
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
|
|
{
|
|
int index = le32_to_cpu(e820_table.count);
|
|
struct e820_entry *entry;
|
|
|
|
if (index >= E820_NR_ENTRIES)
|
|
return -EBUSY;
|
|
entry = &e820_table.entry[index++];
|
|
|
|
entry->address = cpu_to_le64(address);
|
|
entry->length = cpu_to_le64(length);
|
|
entry->type = cpu_to_le32(type);
|
|
|
|
e820_table.count = cpu_to_le32(index);
|
|
return index;
|
|
}
|
|
|
|
static void *bochs_bios_init(void)
|
|
{
|
|
void *fw_cfg;
|
|
uint8_t *smbios_table;
|
|
size_t smbios_len;
|
|
uint64_t *numa_fw_cfg;
|
|
int i, j;
|
|
|
|
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
|
|
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
|
|
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
|
|
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
|
|
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
|
|
|
|
register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
|
|
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
|
|
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
|
|
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
|
|
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
|
|
|
|
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
|
|
acpi_tables_len);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
|
|
|
smbios_table = smbios_get_table(&smbios_len);
|
|
if (smbios_table)
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
|
|
smbios_table, smbios_len);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
|
|
sizeof(struct e820_table));
|
|
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
|
|
sizeof(struct hpet_fw_config));
|
|
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
|
* of nodes, one word for each VCPU->node and one word for each node to
|
|
* hold the amount of memory.
|
|
*/
|
|
numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
|
|
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
|
for (i = 0; i < max_cpus; i++) {
|
|
for (j = 0; j < nb_numa_nodes; j++) {
|
|
if (node_cpumask[j] & (1 << i)) {
|
|
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
for (i = 0; i < nb_numa_nodes; i++) {
|
|
numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
|
}
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
|
|
(1 + max_cpus + nb_numa_nodes) * 8);
|
|
|
|
return fw_cfg;
|
|
}
|
|
|
|
static long get_file_size(FILE *f)
|
|
{
|
|
long where, size;
|
|
|
|
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
|
|
|
where = ftell(f);
|
|
fseek(f, 0, SEEK_END);
|
|
size = ftell(f);
|
|
fseek(f, where, SEEK_SET);
|
|
|
|
return size;
|
|
}
|
|
|
|
static void load_linux(void *fw_cfg,
|
|
const char *kernel_filename,
|
|
const char *initrd_filename,
|
|
const char *kernel_cmdline,
|
|
target_phys_addr_t max_ram_size)
|
|
{
|
|
uint16_t protocol;
|
|
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
|
|
uint32_t initrd_max;
|
|
uint8_t header[8192], *setup, *kernel, *initrd_data;
|
|
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
|
FILE *f;
|
|
char *vmode;
|
|
|
|
/* Align to 16 bytes as a paranoia measure */
|
|
cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
|
|
|
|
/* load the kernel header */
|
|
f = fopen(kernel_filename, "rb");
|
|
if (!f || !(kernel_size = get_file_size(f)) ||
|
|
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
|
MIN(ARRAY_SIZE(header), kernel_size)) {
|
|
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
|
|
kernel_filename, strerror(errno));
|
|
exit(1);
|
|
}
|
|
|
|
/* kernel protocol version */
|
|
#if 0
|
|
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
|
#endif
|
|
if (ldl_p(header+0x202) == 0x53726448)
|
|
protocol = lduw_p(header+0x206);
|
|
else {
|
|
/* This looks like a multiboot kernel. If it is, let's stop
|
|
treating it like a Linux kernel. */
|
|
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
|
|
kernel_cmdline, kernel_size, header))
|
|
return;
|
|
protocol = 0;
|
|
}
|
|
|
|
if (protocol < 0x200 || !(header[0x211] & 0x01)) {
|
|
/* Low kernel */
|
|
real_addr = 0x90000;
|
|
cmdline_addr = 0x9a000 - cmdline_size;
|
|
prot_addr = 0x10000;
|
|
} else if (protocol < 0x202) {
|
|
/* High but ancient kernel */
|
|
real_addr = 0x90000;
|
|
cmdline_addr = 0x9a000 - cmdline_size;
|
|
prot_addr = 0x100000;
|
|
} else {
|
|
/* High and recent kernel */
|
|
real_addr = 0x10000;
|
|
cmdline_addr = 0x20000;
|
|
prot_addr = 0x100000;
|
|
}
|
|
|
|
#if 0
|
|
fprintf(stderr,
|
|
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
|
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
|
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
|
real_addr,
|
|
cmdline_addr,
|
|
prot_addr);
|
|
#endif
|
|
|
|
/* highest address for loading the initrd */
|
|
if (protocol >= 0x203)
|
|
initrd_max = ldl_p(header+0x22c);
|
|
else
|
|
initrd_max = 0x37ffffff;
|
|
|
|
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
|
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
|
|
(uint8_t*)strdup(kernel_cmdline),
|
|
strlen(kernel_cmdline)+1);
|
|
|
|
if (protocol >= 0x202) {
|
|
stl_p(header+0x228, cmdline_addr);
|
|
} else {
|
|
stw_p(header+0x20, 0xA33F);
|
|
stw_p(header+0x22, cmdline_addr-real_addr);
|
|
}
|
|
|
|
/* handle vga= parameter */
|
|
vmode = strstr(kernel_cmdline, "vga=");
|
|
if (vmode) {
|
|
unsigned int video_mode;
|
|
/* skip "vga=" */
|
|
vmode += 4;
|
|
if (!strncmp(vmode, "normal", 6)) {
|
|
video_mode = 0xffff;
|
|
} else if (!strncmp(vmode, "ext", 3)) {
|
|
video_mode = 0xfffe;
|
|
} else if (!strncmp(vmode, "ask", 3)) {
|
|
video_mode = 0xfffd;
|
|
} else {
|
|
video_mode = strtol(vmode, NULL, 0);
|
|
}
|
|
stw_p(header+0x1fa, video_mode);
|
|
}
|
|
|
|
/* loader type */
|
|
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
|
If this code is substantially changed, you may want to consider
|
|
incrementing the revision. */
|
|
if (protocol >= 0x200)
|
|
header[0x210] = 0xB0;
|
|
|
|
/* heap */
|
|
if (protocol >= 0x201) {
|
|
header[0x211] |= 0x80; /* CAN_USE_HEAP */
|
|
stw_p(header+0x224, cmdline_addr-real_addr-0x200);
|
|
}
|
|
|
|
/* load initrd */
|
|
if (initrd_filename) {
|
|
if (protocol < 0x200) {
|
|
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
|
exit(1);
|
|
}
|
|
|
|
initrd_size = get_image_size(initrd_filename);
|
|
if (initrd_size < 0) {
|
|
fprintf(stderr, "qemu: error reading initrd %s\n",
|
|
initrd_filename);
|
|
exit(1);
|
|
}
|
|
|
|
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
|
|
|
initrd_data = g_malloc(initrd_size);
|
|
load_image(initrd_filename, initrd_data);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
|
|
|
|
stl_p(header+0x218, initrd_addr);
|
|
stl_p(header+0x21c, initrd_size);
|
|
}
|
|
|
|
/* load kernel and setup */
|
|
setup_size = header[0x1f1];
|
|
if (setup_size == 0)
|
|
setup_size = 4;
|
|
setup_size = (setup_size+1)*512;
|
|
kernel_size -= setup_size;
|
|
|
|
setup = g_malloc(setup_size);
|
|
kernel = g_malloc(kernel_size);
|
|
fseek(f, 0, SEEK_SET);
|
|
if (fread(setup, 1, setup_size, f) != setup_size) {
|
|
fprintf(stderr, "fread() failed\n");
|
|
exit(1);
|
|
}
|
|
if (fread(kernel, 1, kernel_size, f) != kernel_size) {
|
|
fprintf(stderr, "fread() failed\n");
|
|
exit(1);
|
|
}
|
|
fclose(f);
|
|
memcpy(setup, header, MIN(sizeof(header), setup_size));
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
|
|
|
|
option_rom[nb_option_roms].name = "linuxboot.bin";
|
|
option_rom[nb_option_roms].bootindex = 0;
|
|
nb_option_roms++;
|
|
}
|
|
|
|
#define NE2000_NB_MAX 6
|
|
|
|
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
|
|
0x280, 0x380 };
|
|
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
|
|
|
|
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
|
|
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
|
|
|
|
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
|
|
{
|
|
static int nb_ne2k = 0;
|
|
|
|
if (nb_ne2k == NE2000_NB_MAX)
|
|
return;
|
|
isa_ne2000_init(bus, ne2000_io[nb_ne2k],
|
|
ne2000_irq[nb_ne2k], nd);
|
|
nb_ne2k++;
|
|
}
|
|
|
|
int cpu_is_bsp(CPUState *env)
|
|
{
|
|
/* We hard-wire the BSP to the first CPU. */
|
|
return env->cpu_index == 0;
|
|
}
|
|
|
|
DeviceState *cpu_get_current_apic(void)
|
|
{
|
|
if (cpu_single_env) {
|
|
return cpu_single_env->apic_state;
|
|
} else {
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
static DeviceState *apic_init(void *env, uint8_t apic_id)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *d;
|
|
static int apic_mapped;
|
|
|
|
dev = qdev_create(NULL, "apic");
|
|
qdev_prop_set_uint8(dev, "id", apic_id);
|
|
qdev_prop_set_ptr(dev, "cpu_env", env);
|
|
qdev_init_nofail(dev);
|
|
d = sysbus_from_qdev(dev);
|
|
|
|
/* XXX: mapping more APICs at the same memory location */
|
|
if (apic_mapped == 0) {
|
|
/* NOTE: the APIC is directly connected to the CPU - it is not
|
|
on the global memory bus. */
|
|
/* XXX: what if the base changes? */
|
|
sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
|
|
apic_mapped = 1;
|
|
}
|
|
|
|
msix_supported = 1;
|
|
|
|
return dev;
|
|
}
|
|
|
|
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
|
BIOS will read it and start S3 resume at POST Entry */
|
|
void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
|
|
{
|
|
ISADevice *s = opaque;
|
|
|
|
if (level) {
|
|
rtc_set_memory(s, 0xF, 0xFE);
|
|
}
|
|
}
|
|
|
|
void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
|
|
{
|
|
CPUState *s = opaque;
|
|
|
|
if (level) {
|
|
cpu_interrupt(s, CPU_INTERRUPT_SMI);
|
|
}
|
|
}
|
|
|
|
static void pc_cpu_reset(void *opaque)
|
|
{
|
|
CPUState *env = opaque;
|
|
|
|
cpu_reset(env);
|
|
env->halted = !cpu_is_bsp(env);
|
|
}
|
|
|
|
static CPUState *pc_new_cpu(const char *cpu_model)
|
|
{
|
|
CPUState *env;
|
|
|
|
env = cpu_init(cpu_model);
|
|
if (!env) {
|
|
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
|
exit(1);
|
|
}
|
|
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
|
|
env->apic_state = apic_init(env, env->cpuid_apic_id);
|
|
}
|
|
qemu_register_reset(pc_cpu_reset, env);
|
|
pc_cpu_reset(env);
|
|
return env;
|
|
}
|
|
|
|
void pc_cpus_init(const char *cpu_model)
|
|
{
|
|
int i;
|
|
|
|
/* init CPUs */
|
|
if (cpu_model == NULL) {
|
|
#ifdef TARGET_X86_64
|
|
cpu_model = "qemu64";
|
|
#else
|
|
cpu_model = "qemu32";
|
|
#endif
|
|
}
|
|
|
|
for(i = 0; i < smp_cpus; i++) {
|
|
pc_new_cpu(cpu_model);
|
|
}
|
|
}
|
|
|
|
void pc_memory_init(MemoryRegion *system_memory,
|
|
const char *kernel_filename,
|
|
const char *kernel_cmdline,
|
|
const char *initrd_filename,
|
|
ram_addr_t below_4g_mem_size,
|
|
ram_addr_t above_4g_mem_size,
|
|
MemoryRegion *rom_memory,
|
|
MemoryRegion **ram_memory)
|
|
{
|
|
char *filename;
|
|
int ret, linux_boot, i;
|
|
MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
|
|
MemoryRegion *ram_below_4g, *ram_above_4g;
|
|
int bios_size, isa_bios_size;
|
|
void *fw_cfg;
|
|
|
|
linux_boot = (kernel_filename != NULL);
|
|
|
|
/* Allocate RAM. We allocate it as a single memory region and use
|
|
* aliases to address portions of it, mostly for backwards compatibility
|
|
* with older qemus that used qemu_ram_alloc().
|
|
*/
|
|
ram = g_malloc(sizeof(*ram));
|
|
memory_region_init_ram(ram, "pc.ram",
|
|
below_4g_mem_size + above_4g_mem_size);
|
|
vmstate_register_ram_global(ram);
|
|
*ram_memory = ram;
|
|
ram_below_4g = g_malloc(sizeof(*ram_below_4g));
|
|
memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
|
|
0, below_4g_mem_size);
|
|
memory_region_add_subregion(system_memory, 0, ram_below_4g);
|
|
if (above_4g_mem_size > 0) {
|
|
ram_above_4g = g_malloc(sizeof(*ram_above_4g));
|
|
memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
|
|
below_4g_mem_size, above_4g_mem_size);
|
|
memory_region_add_subregion(system_memory, 0x100000000ULL,
|
|
ram_above_4g);
|
|
}
|
|
|
|
/* BIOS load */
|
|
if (bios_name == NULL)
|
|
bios_name = BIOS_FILENAME;
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
if (filename) {
|
|
bios_size = get_image_size(filename);
|
|
} else {
|
|
bios_size = -1;
|
|
}
|
|
if (bios_size <= 0 ||
|
|
(bios_size % 65536) != 0) {
|
|
goto bios_error;
|
|
}
|
|
bios = g_malloc(sizeof(*bios));
|
|
memory_region_init_ram(bios, "pc.bios", bios_size);
|
|
vmstate_register_ram_global(bios);
|
|
memory_region_set_readonly(bios, true);
|
|
ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
|
|
if (ret != 0) {
|
|
bios_error:
|
|
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
|
exit(1);
|
|
}
|
|
if (filename) {
|
|
g_free(filename);
|
|
}
|
|
/* map the last 128KB of the BIOS in ISA space */
|
|
isa_bios_size = bios_size;
|
|
if (isa_bios_size > (128 * 1024))
|
|
isa_bios_size = 128 * 1024;
|
|
isa_bios = g_malloc(sizeof(*isa_bios));
|
|
memory_region_init_alias(isa_bios, "isa-bios", bios,
|
|
bios_size - isa_bios_size, isa_bios_size);
|
|
memory_region_add_subregion_overlap(rom_memory,
|
|
0x100000 - isa_bios_size,
|
|
isa_bios,
|
|
1);
|
|
memory_region_set_readonly(isa_bios, true);
|
|
|
|
option_rom_mr = g_malloc(sizeof(*option_rom_mr));
|
|
memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
|
|
vmstate_register_ram_global(option_rom_mr);
|
|
memory_region_add_subregion_overlap(rom_memory,
|
|
PC_ROM_MIN_VGA,
|
|
option_rom_mr,
|
|
1);
|
|
|
|
/* map all the bios at the top of memory */
|
|
memory_region_add_subregion(rom_memory,
|
|
(uint32_t)(-bios_size),
|
|
bios);
|
|
|
|
fw_cfg = bochs_bios_init();
|
|
rom_set_fw(fw_cfg);
|
|
|
|
if (linux_boot) {
|
|
load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
|
|
}
|
|
|
|
for (i = 0; i < nb_option_roms; i++) {
|
|
rom_add_option(option_rom[i].name, option_rom[i].bootindex);
|
|
}
|
|
}
|
|
|
|
qemu_irq *pc_allocate_cpu_irq(void)
|
|
{
|
|
return qemu_allocate_irqs(pic_irq_request, NULL, 1);
|
|
}
|
|
|
|
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
|
|
{
|
|
DeviceState *dev = NULL;
|
|
|
|
if (cirrus_vga_enabled) {
|
|
if (pci_bus) {
|
|
dev = pci_cirrus_vga_init(pci_bus);
|
|
} else {
|
|
dev = isa_cirrus_vga_init(get_system_memory());
|
|
}
|
|
} else if (vmsvga_enabled) {
|
|
if (pci_bus) {
|
|
dev = pci_vmsvga_init(pci_bus);
|
|
if (!dev) {
|
|
fprintf(stderr, "Warning: vmware_vga not available,"
|
|
" using standard VGA instead\n");
|
|
dev = pci_vga_init(pci_bus);
|
|
}
|
|
} else {
|
|
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
|
}
|
|
#ifdef CONFIG_SPICE
|
|
} else if (qxl_enabled) {
|
|
if (pci_bus) {
|
|
dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
|
|
} else {
|
|
fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
|
|
}
|
|
#endif
|
|
} else if (std_vga_enabled) {
|
|
if (pci_bus) {
|
|
dev = pci_vga_init(pci_bus);
|
|
} else {
|
|
dev = isa_vga_init(isa_bus);
|
|
}
|
|
}
|
|
|
|
return dev;
|
|
}
|
|
|
|
static void cpu_request_exit(void *opaque, int irq, int level)
|
|
{
|
|
CPUState *env = cpu_single_env;
|
|
|
|
if (env && level) {
|
|
cpu_exit(env);
|
|
}
|
|
}
|
|
|
|
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
|
|
ISADevice **rtc_state,
|
|
ISADevice **floppy,
|
|
bool no_vmport)
|
|
{
|
|
int i;
|
|
DriveInfo *fd[MAX_FD];
|
|
qemu_irq rtc_irq = NULL;
|
|
qemu_irq *a20_line;
|
|
ISADevice *i8042, *port92, *vmmouse, *pit;
|
|
qemu_irq *cpu_exit_irq;
|
|
|
|
register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
|
|
|
|
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
|
|
|
|
if (!no_hpet) {
|
|
DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
|
|
|
|
if (hpet) {
|
|
for (i = 0; i < GSI_NUM_PINS; i++) {
|
|
sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
|
|
}
|
|
rtc_irq = qdev_get_gpio_in(hpet, 0);
|
|
}
|
|
}
|
|
*rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
|
|
|
|
qemu_register_boot_set(pc_boot_set, *rtc_state);
|
|
|
|
pit = pit_init(isa_bus, 0x40, 0);
|
|
pcspk_init(pit);
|
|
|
|
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
|
|
if (serial_hds[i]) {
|
|
serial_isa_init(isa_bus, i, serial_hds[i]);
|
|
}
|
|
}
|
|
|
|
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
|
|
if (parallel_hds[i]) {
|
|
parallel_init(isa_bus, i, parallel_hds[i]);
|
|
}
|
|
}
|
|
|
|
a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
|
|
i8042 = isa_create_simple(isa_bus, "i8042");
|
|
i8042_setup_a20_line(i8042, &a20_line[0]);
|
|
if (!no_vmport) {
|
|
vmport_init(isa_bus);
|
|
vmmouse = isa_try_create(isa_bus, "vmmouse");
|
|
} else {
|
|
vmmouse = NULL;
|
|
}
|
|
if (vmmouse) {
|
|
qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
|
|
qdev_init_nofail(&vmmouse->qdev);
|
|
}
|
|
port92 = isa_create_simple(isa_bus, "port92");
|
|
port92_init(port92, &a20_line[1]);
|
|
|
|
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
|
|
DMA_init(0, cpu_exit_irq);
|
|
|
|
for(i = 0; i < MAX_FD; i++) {
|
|
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
|
}
|
|
*floppy = fdctrl_init_isa(isa_bus, fd);
|
|
}
|
|
|
|
void pc_pci_device_init(PCIBus *pci_bus)
|
|
{
|
|
int max_bus;
|
|
int bus;
|
|
|
|
max_bus = drive_get_max_bus(IF_SCSI);
|
|
for (bus = 0; bus <= max_bus; bus++) {
|
|
pci_create_simple(pci_bus, -1, "lsi53c895a");
|
|
}
|
|
}
|