Lijun Pan f3e0d864ab target/ppc: add vmulh{su}w instructions ... vmulhsw: Vector Multiply High Signed Word vmulhuw: Vector Multiply High Unsigned Word Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Message-Id: <20200724045845.89976-4-ljp@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>		2020-08-12 13:16:27 +10:00
..
dfp-impl.inc.c	target/ppc: move FP and VMX registers into aligned vsr register array	2019-01-09 09:28:14 +11:00
dfp-ops.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
fp-impl.inc.c	target/ppc: Fix typo in comments	2020-02-21 09:15:04 +11:00
fp-ops.inc.c	ppc: Add support for 'mffsce' instruction	2019-10-04 10:25:23 +10:00
spe-impl.inc.c	target/ppc: Fix TCG leak with the evmwsmiaa instruction	2020-08-12 13:16:27 +10:00
spe-ops.inc.c	Move target-* CPU file into a target/ folder	2016-12-20 21:52:12 +01:00
vmx-impl.inc.c	target/ppc: add vmulh{su}w instructions	2020-08-12 13:16:27 +10:00
vmx-ops.inc.c	target/ppc: add vmulh{su}w instructions	2020-08-12 13:16:27 +10:00
vsx-impl.inc.c	target/ppc: Use tcg_gen_gvec_dup_imm	2020-05-06 09:25:01 -07:00
vsx-ops.inc.c	target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro	2019-07-02 09:43:58 +10:00