i386 is the first user of AccelCPUClass, allowing to split
cpu.c into:
cpu.c cpuid and common x86 cpu functionality
host-cpu.c host x86 cpu functions and "host" cpu type
kvm/kvm-cpu.c KVM x86 AccelCPUClass
hvf/hvf-cpu.c HVF x86 AccelCPUClass
tcg/tcg-cpu.c TCG x86 AccelCPUClass
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio]:
Rebased on commit b8184135
("target/i386: allow modifying TCG phys-addr-bits")
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210322132800.7470-5-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
202 lines
5.7 KiB
C
202 lines
5.7 KiB
C
/*
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* x86 host CPU functions, and "host" cpu type initialization
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*
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* Copyright 2021 SUSE LLC
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "host-cpu.h"
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#include "qapi/error.h"
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#include "sysemu/sysemu.h"
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/* Note: Only safe for use on x86(-64) hosts */
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static uint32_t host_cpu_phys_bits(void)
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{
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uint32_t eax;
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uint32_t host_phys_bits;
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host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
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if (eax >= 0x80000008) {
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host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
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/*
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* Note: According to AMD doc 25481 rev 2.34 they have a field
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* at 23:16 that can specify a maximum physical address bits for
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* the guest that can override this value; but I've not seen
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* anything with that set.
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*/
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host_phys_bits = eax & 0xff;
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} else {
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/*
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* It's an odd 64 bit machine that doesn't have the leaf for
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* physical address bits; fall back to 36 that's most older
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* Intel.
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*/
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host_phys_bits = 36;
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}
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return host_phys_bits;
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}
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static void host_cpu_enable_cpu_pm(X86CPU *cpu)
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{
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CPUX86State *env = &cpu->env;
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host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
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&cpu->mwait.ecx, &cpu->mwait.edx);
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env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
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}
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static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp)
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{
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uint32_t host_phys_bits = host_cpu_phys_bits();
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uint32_t phys_bits = cpu->phys_bits;
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static bool warned;
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/*
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* Print a warning if the user set it to a value that's not the
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* host value.
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*/
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if (phys_bits != host_phys_bits && phys_bits != 0 &&
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!warned) {
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warn_report("Host physical bits (%u)"
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" does not match phys-bits property (%u)",
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host_phys_bits, phys_bits);
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warned = true;
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}
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if (cpu->host_phys_bits) {
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/* The user asked for us to use the host physical bits */
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phys_bits = host_phys_bits;
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if (cpu->host_phys_bits_limit &&
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phys_bits > cpu->host_phys_bits_limit) {
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phys_bits = cpu->host_phys_bits_limit;
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}
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}
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if (phys_bits &&
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(phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
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phys_bits < 32)) {
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error_setg(errp, "phys-bits should be between 32 and %u "
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" (but is %u)",
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TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
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}
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return phys_bits;
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}
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void host_cpu_realizefn(CPUState *cs, Error **errp)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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if (cpu->max_features && enable_cpu_pm) {
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host_cpu_enable_cpu_pm(cpu);
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}
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
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cpu->phys_bits = host_cpu_adjust_phys_bits(cpu, errp);
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}
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}
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#define CPUID_MODEL_ID_SZ 48
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/**
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* cpu_x86_fill_model_id:
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* Get CPUID model ID string from host CPU.
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*
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* @str should have at least CPUID_MODEL_ID_SZ bytes
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*
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* The function does NOT add a null terminator to the string
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* automatically.
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*/
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static int host_cpu_fill_model_id(char *str)
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{
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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int i;
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for (i = 0; i < 3; i++) {
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host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
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memcpy(str + i * 16 + 0, &eax, 4);
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memcpy(str + i * 16 + 4, &ebx, 4);
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memcpy(str + i * 16 + 8, &ecx, 4);
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memcpy(str + i * 16 + 12, &edx, 4);
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}
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return 0;
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}
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void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping)
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{
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uint32_t eax, ebx, ecx, edx;
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host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
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x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
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host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
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if (family) {
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*family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
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}
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if (model) {
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*model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
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}
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if (stepping) {
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*stepping = eax & 0x0F;
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}
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}
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void host_cpu_instance_init(X86CPU *cpu)
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{
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uint32_t ebx = 0, ecx = 0, edx = 0;
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char vendor[CPUID_VENDOR_SZ + 1];
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host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
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x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
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object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
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}
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void host_cpu_max_instance_init(X86CPU *cpu)
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{
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char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
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char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
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int family, model, stepping;
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/* Use max host physical address bits if -cpu max option is applied */
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object_property_set_bool(OBJECT(cpu), "host-phys-bits", true, &error_abort);
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host_cpu_vendor_fms(vendor, &family, &model, &stepping);
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host_cpu_fill_model_id(model_id);
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object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
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object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
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object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
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object_property_set_int(OBJECT(cpu), "stepping", stepping,
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&error_abort);
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object_property_set_str(OBJECT(cpu), "model-id", model_id,
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&error_abort);
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}
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static void host_cpu_class_init(ObjectClass *oc, void *data)
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{
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X86CPUClass *xcc = X86_CPU_CLASS(oc);
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xcc->host_cpuid_required = true;
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xcc->ordering = 8;
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xcc->model_description =
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g_strdup_printf("processor with all supported host features ");
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}
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static const TypeInfo host_cpu_type_info = {
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.name = X86_CPU_TYPE_NAME("host"),
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.parent = X86_CPU_TYPE_NAME("max"),
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.class_init = host_cpu_class_init,
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};
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static void host_cpu_type_init(void)
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{
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type_register_static(&host_cpu_type_info);
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}
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type_init(host_cpu_type_init);
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