f7697f0e62
Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-3-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
75 lines
2.9 KiB
C
75 lines
2.9 KiB
C
/*
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* RISC-V VMState Description
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*
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* Copyright (c) 2020 Huawei Technologies Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "migration/cpu.h"
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const VMStateDescription vmstate_riscv_cpu = {
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.name = "cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
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VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
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VMSTATE_UINTTL(env.pc, RISCVCPU),
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VMSTATE_UINTTL(env.load_res, RISCVCPU),
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VMSTATE_UINTTL(env.load_val, RISCVCPU),
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VMSTATE_UINTTL(env.frm, RISCVCPU),
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VMSTATE_UINTTL(env.badaddr, RISCVCPU),
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VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
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VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
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VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
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VMSTATE_UINTTL(env.misa, RISCVCPU),
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VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
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VMSTATE_UINT32(env.features, RISCVCPU),
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VMSTATE_UINTTL(env.priv, RISCVCPU),
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VMSTATE_UINTTL(env.virt, RISCVCPU),
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VMSTATE_UINTTL(env.resetvec, RISCVCPU),
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VMSTATE_UINTTL(env.mhartid, RISCVCPU),
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VMSTATE_UINT64(env.mstatus, RISCVCPU),
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VMSTATE_UINTTL(env.mip, RISCVCPU),
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VMSTATE_UINT32(env.miclaim, RISCVCPU),
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VMSTATE_UINTTL(env.mie, RISCVCPU),
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VMSTATE_UINTTL(env.mideleg, RISCVCPU),
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VMSTATE_UINTTL(env.sptbr, RISCVCPU),
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VMSTATE_UINTTL(env.satp, RISCVCPU),
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VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
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VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
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VMSTATE_UINTTL(env.medeleg, RISCVCPU),
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VMSTATE_UINTTL(env.stvec, RISCVCPU),
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VMSTATE_UINTTL(env.sepc, RISCVCPU),
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VMSTATE_UINTTL(env.scause, RISCVCPU),
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VMSTATE_UINTTL(env.mtvec, RISCVCPU),
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VMSTATE_UINTTL(env.mepc, RISCVCPU),
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VMSTATE_UINTTL(env.mcause, RISCVCPU),
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VMSTATE_UINTTL(env.mtval, RISCVCPU),
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VMSTATE_UINTTL(env.scounteren, RISCVCPU),
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VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
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VMSTATE_UINTTL(env.sscratch, RISCVCPU),
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VMSTATE_UINTTL(env.mscratch, RISCVCPU),
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VMSTATE_UINT64(env.mfromhost, RISCVCPU),
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VMSTATE_UINT64(env.mtohost, RISCVCPU),
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VMSTATE_UINT64(env.timecmp, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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