The machine that with hvf accelerator and smp sometimes boot hangs because all processors are executing instructions at startup, including early I/O emulations. We should just allow the bootstrap processor to initialize the machine and then to wake up slave processors by interrupt. Signed-off-by: Heiher <r@hev.cc> Message-Id: <20190123073402.28465-1-r@hev.cc> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
971 lines
29 KiB
C
971 lines
29 KiB
C
/* Copyright 2008 IBM Corporation
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* 2008 Red Hat, Inc.
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* Copyright 2011 Intel Corporation
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* Copyright 2016 Veertu, Inc.
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* Copyright 2017 The Android Open Source Project
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*
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* QEMU Hypervisor.framework support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* This file contain code under public domain from the hvdos project:
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* https://github.com/mist64/hvdos
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*
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* Parts Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "sysemu/hvf.h"
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#include "hvf-i386.h"
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#include "vmcs.h"
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#include "vmx.h"
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#include "x86.h"
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#include "x86_descr.h"
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#include "x86_mmu.h"
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#include "x86_decode.h"
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#include "x86_emu.h"
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#include "x86_task.h"
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#include "x86hvf.h"
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#include <Hypervisor/hv.h>
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#include <Hypervisor/hv_vmx.h>
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#include "exec/address-spaces.h"
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#include "hw/i386/apic_internal.h"
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#include "hw/boards.h"
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#include "qemu/main-loop.h"
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#include "sysemu/accel.h"
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#include "sysemu/sysemu.h"
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#include "target/i386/cpu.h"
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HVFState *hvf_state;
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static void assert_hvf_ok(hv_return_t ret)
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{
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if (ret == HV_SUCCESS) {
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return;
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}
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switch (ret) {
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case HV_ERROR:
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error_report("Error: HV_ERROR");
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break;
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case HV_BUSY:
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error_report("Error: HV_BUSY");
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break;
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case HV_BAD_ARGUMENT:
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error_report("Error: HV_BAD_ARGUMENT");
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break;
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case HV_NO_RESOURCES:
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error_report("Error: HV_NO_RESOURCES");
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break;
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case HV_NO_DEVICE:
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error_report("Error: HV_NO_DEVICE");
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break;
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case HV_UNSUPPORTED:
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error_report("Error: HV_UNSUPPORTED");
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break;
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default:
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error_report("Unknown Error");
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}
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abort();
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}
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/* Memory slots */
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hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t end)
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{
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hvf_slot *slot;
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int x;
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for (x = 0; x < hvf_state->num_slots; ++x) {
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slot = &hvf_state->slots[x];
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if (slot->size && start < (slot->start + slot->size) &&
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end > slot->start) {
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return slot;
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}
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}
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return NULL;
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}
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struct mac_slot {
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int present;
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uint64_t size;
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uint64_t gpa_start;
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uint64_t gva;
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};
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struct mac_slot mac_slots[32];
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#define ALIGN(x, y) (((x) + (y) - 1) & ~((y) - 1))
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static int do_hvf_set_memory(hvf_slot *slot)
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{
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struct mac_slot *macslot;
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hv_memory_flags_t flags;
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hv_return_t ret;
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macslot = &mac_slots[slot->slot_id];
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if (macslot->present) {
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if (macslot->size != slot->size) {
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macslot->present = 0;
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ret = hv_vm_unmap(macslot->gpa_start, macslot->size);
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assert_hvf_ok(ret);
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}
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}
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if (!slot->size) {
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return 0;
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}
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flags = HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC;
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macslot->present = 1;
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macslot->gpa_start = slot->start;
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macslot->size = slot->size;
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ret = hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, flags);
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assert_hvf_ok(ret);
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return 0;
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}
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void hvf_set_phys_mem(MemoryRegionSection *section, bool add)
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{
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hvf_slot *mem;
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MemoryRegion *area = section->mr;
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if (!memory_region_is_ram(area)) {
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return;
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}
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mem = hvf_find_overlap_slot(
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section->offset_within_address_space,
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section->offset_within_address_space + int128_get64(section->size));
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if (mem && add) {
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if (mem->size == int128_get64(section->size) &&
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mem->start == section->offset_within_address_space &&
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mem->mem == (memory_region_get_ram_ptr(area) +
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section->offset_within_region)) {
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return; /* Same region was attempted to register, go away. */
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}
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}
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/* Region needs to be reset. set the size to 0 and remap it. */
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if (mem) {
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mem->size = 0;
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if (do_hvf_set_memory(mem)) {
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error_report("Failed to reset overlapping slot");
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abort();
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}
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}
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if (!add) {
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return;
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}
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/* Now make a new slot. */
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int x;
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for (x = 0; x < hvf_state->num_slots; ++x) {
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mem = &hvf_state->slots[x];
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if (!mem->size) {
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break;
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}
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}
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if (x == hvf_state->num_slots) {
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error_report("No free slots");
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abort();
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}
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mem->size = int128_get64(section->size);
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mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region;
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mem->start = section->offset_within_address_space;
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mem->region = area;
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if (do_hvf_set_memory(mem)) {
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error_report("Error registering new memory slot");
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abort();
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}
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}
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void vmx_update_tpr(CPUState *cpu)
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{
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/* TODO: need integrate APIC handling */
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X86CPU *x86_cpu = X86_CPU(cpu);
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int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
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int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
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wreg(cpu->hvf_fd, HV_X86_TPR, tpr);
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if (irr == -1) {
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wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
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} else {
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wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :
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irr >> 4);
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}
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}
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void update_apic_tpr(CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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int tpr = rreg(cpu->hvf_fd, HV_X86_TPR) >> 4;
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cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
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}
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#define VECTORING_INFO_VECTOR_MASK 0xff
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static void hvf_handle_interrupt(CPUState * cpu, int mask)
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{
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cpu->interrupt_request |= mask;
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if (!qemu_cpu_is_self(cpu)) {
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qemu_cpu_kick(cpu);
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}
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}
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void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer,
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int direction, int size, int count)
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{
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int i;
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uint8_t *ptr = buffer;
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for (i = 0; i < count; i++) {
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address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED,
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ptr, size,
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direction);
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ptr += size;
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}
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}
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/* TODO: synchronize vcpu state */
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static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
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{
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CPUState *cpu_state = cpu;
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if (cpu_state->vcpu_dirty == 0) {
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hvf_get_registers(cpu_state);
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}
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cpu_state->vcpu_dirty = 1;
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}
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void hvf_cpu_synchronize_state(CPUState *cpu_state)
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{
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if (cpu_state->vcpu_dirty == 0) {
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run_on_cpu(cpu_state, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
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}
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}
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static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
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{
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CPUState *cpu_state = cpu;
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hvf_put_registers(cpu_state);
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cpu_state->vcpu_dirty = false;
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}
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void hvf_cpu_synchronize_post_reset(CPUState *cpu_state)
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{
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run_on_cpu(cpu_state, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
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}
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void _hvf_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
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{
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CPUState *cpu_state = cpu;
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hvf_put_registers(cpu_state);
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cpu_state->vcpu_dirty = false;
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}
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void hvf_cpu_synchronize_post_init(CPUState *cpu_state)
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{
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run_on_cpu(cpu_state, _hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
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}
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static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual)
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{
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int read, write;
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/* EPT fault on an instruction fetch doesn't make sense here */
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if (ept_qual & EPT_VIOLATION_INST_FETCH) {
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return false;
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}
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/* EPT fault must be a read fault or a write fault */
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read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
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write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
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if ((read | write) == 0) {
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return false;
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}
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if (write && slot) {
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if (slot->flags & HVF_SLOT_LOG) {
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memory_region_set_dirty(slot->region, gpa - slot->start, 1);
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hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
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HV_MEMORY_READ | HV_MEMORY_WRITE);
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}
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}
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/*
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* The EPT violation must have been caused by accessing a
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* guest-physical address that is a translation of a guest-linear
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* address.
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*/
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if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
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(ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
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return false;
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}
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return !slot;
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}
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static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on)
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{
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hvf_slot *slot;
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slot = hvf_find_overlap_slot(
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section->offset_within_address_space,
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section->offset_within_address_space + int128_get64(section->size));
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/* protect region against writes; begin tracking it */
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if (on) {
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slot->flags |= HVF_SLOT_LOG;
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hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
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HV_MEMORY_READ);
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/* stop tracking region*/
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} else {
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slot->flags &= ~HVF_SLOT_LOG;
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hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
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HV_MEMORY_READ | HV_MEMORY_WRITE);
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}
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}
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static void hvf_log_start(MemoryListener *listener,
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MemoryRegionSection *section, int old, int new)
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{
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if (old != 0) {
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return;
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}
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hvf_set_dirty_tracking(section, 1);
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}
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static void hvf_log_stop(MemoryListener *listener,
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MemoryRegionSection *section, int old, int new)
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{
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if (new != 0) {
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return;
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}
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hvf_set_dirty_tracking(section, 0);
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}
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static void hvf_log_sync(MemoryListener *listener,
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MemoryRegionSection *section)
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{
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/*
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* sync of dirty pages is handled elsewhere; just make sure we keep
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* tracking the region.
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*/
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hvf_set_dirty_tracking(section, 1);
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}
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static void hvf_region_add(MemoryListener *listener,
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MemoryRegionSection *section)
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{
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hvf_set_phys_mem(section, true);
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}
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static void hvf_region_del(MemoryListener *listener,
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MemoryRegionSection *section)
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{
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hvf_set_phys_mem(section, false);
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}
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static MemoryListener hvf_memory_listener = {
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.priority = 10,
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.region_add = hvf_region_add,
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.region_del = hvf_region_del,
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.log_start = hvf_log_start,
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.log_stop = hvf_log_stop,
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.log_sync = hvf_log_sync,
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};
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void hvf_reset_vcpu(CPUState *cpu) {
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/* TODO: this shouldn't be needed; there is already a call to
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* cpu_synchronize_all_post_reset in vl.c
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*/
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wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, 0);
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macvm_set_cr0(cpu->hvf_fd, 0x60000010);
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wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK);
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wvmcs(cpu->hvf_fd, VMCS_CR4_SHADOW, 0x0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_CR4, CR4_VMXE_MASK);
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/* set VMCS guest state fields */
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wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_SELECTOR, 0xf000);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_LIMIT, 0xffff);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_ACCESS_RIGHTS, 0x9b);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_BASE, 0xffff0000);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_LIMIT, 0xffff);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_ACCESS_RIGHTS, 0x93);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_BASE, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_LIMIT, 0xffff);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_ACCESS_RIGHTS, 0x93);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_BASE, 0);
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|
wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_LIMIT, 0xffff);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_ACCESS_RIGHTS, 0x93);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_LIMIT, 0xffff);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_ACCESS_RIGHTS, 0x93);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_LIMIT, 0xffff);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_ACCESS_RIGHTS, 0x93);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_BASE, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x10000);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_SELECTOR, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_LIMIT, 0);
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wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_ACCESS_RIGHTS, 0x83);
|
|
wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_BASE, 0);
|
|
|
|
wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT, 0);
|
|
wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE, 0);
|
|
|
|
wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT, 0);
|
|
wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE, 0);
|
|
|
|
/*wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);*/
|
|
wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, 0x0);
|
|
|
|
wreg(cpu->hvf_fd, HV_X86_RIP, 0xfff0);
|
|
wreg(cpu->hvf_fd, HV_X86_RDX, 0x623);
|
|
wreg(cpu->hvf_fd, HV_X86_RFLAGS, 0x2);
|
|
wreg(cpu->hvf_fd, HV_X86_RSP, 0x0);
|
|
wreg(cpu->hvf_fd, HV_X86_RAX, 0x0);
|
|
wreg(cpu->hvf_fd, HV_X86_RBX, 0x0);
|
|
wreg(cpu->hvf_fd, HV_X86_RCX, 0x0);
|
|
wreg(cpu->hvf_fd, HV_X86_RSI, 0x0);
|
|
wreg(cpu->hvf_fd, HV_X86_RDI, 0x0);
|
|
wreg(cpu->hvf_fd, HV_X86_RBP, 0x0);
|
|
|
|
for (int i = 0; i < 8; i++) {
|
|
wreg(cpu->hvf_fd, HV_X86_R8 + i, 0x0);
|
|
}
|
|
|
|
hv_vm_sync_tsc(0);
|
|
hv_vcpu_invalidate_tlb(cpu->hvf_fd);
|
|
hv_vcpu_flush(cpu->hvf_fd);
|
|
}
|
|
|
|
void hvf_vcpu_destroy(CPUState *cpu)
|
|
{
|
|
hv_return_t ret = hv_vcpu_destroy((hv_vcpuid_t)cpu->hvf_fd);
|
|
assert_hvf_ok(ret);
|
|
}
|
|
|
|
static void dummy_signal(int sig)
|
|
{
|
|
}
|
|
|
|
int hvf_init_vcpu(CPUState *cpu)
|
|
{
|
|
|
|
X86CPU *x86cpu = X86_CPU(cpu);
|
|
CPUX86State *env = &x86cpu->env;
|
|
int r;
|
|
|
|
/* init cpu signals */
|
|
sigset_t set;
|
|
struct sigaction sigact;
|
|
|
|
memset(&sigact, 0, sizeof(sigact));
|
|
sigact.sa_handler = dummy_signal;
|
|
sigaction(SIG_IPI, &sigact, NULL);
|
|
|
|
pthread_sigmask(SIG_BLOCK, NULL, &set);
|
|
sigdelset(&set, SIG_IPI);
|
|
|
|
init_emu();
|
|
init_decoder();
|
|
|
|
hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1);
|
|
env->hvf_emul = g_new0(HVFX86EmulatorState, 1);
|
|
|
|
r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);
|
|
cpu->vcpu_dirty = 1;
|
|
assert_hvf_ok(r);
|
|
|
|
if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED,
|
|
&hvf_state->hvf_caps->vmx_cap_pinbased)) {
|
|
abort();
|
|
}
|
|
if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED,
|
|
&hvf_state->hvf_caps->vmx_cap_procbased)) {
|
|
abort();
|
|
}
|
|
if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2,
|
|
&hvf_state->hvf_caps->vmx_cap_procbased2)) {
|
|
abort();
|
|
}
|
|
if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY,
|
|
&hvf_state->hvf_caps->vmx_cap_entry)) {
|
|
abort();
|
|
}
|
|
|
|
/* set VMCS control fields */
|
|
wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS,
|
|
cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,
|
|
VMCS_PIN_BASED_CTLS_EXTINT |
|
|
VMCS_PIN_BASED_CTLS_NMI |
|
|
VMCS_PIN_BASED_CTLS_VNMI));
|
|
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS,
|
|
cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
|
|
VMCS_PRI_PROC_BASED_CTLS_HLT |
|
|
VMCS_PRI_PROC_BASED_CTLS_MWAIT |
|
|
VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
|
|
VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
|
|
VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
|
|
wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,
|
|
cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,
|
|
VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
|
|
|
|
wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
|
|
0));
|
|
wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
|
|
|
|
wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
|
|
|
|
x86cpu = X86_CPU(cpu);
|
|
x86cpu->env.xsave_buf = qemu_memalign(4096, 4096);
|
|
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1);
|
|
/*hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);*/
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1);
|
|
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info)
|
|
{
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
CPUX86State *env = &x86_cpu->env;
|
|
|
|
env->exception_injected = -1;
|
|
env->interrupt_injected = -1;
|
|
env->nmi_injected = false;
|
|
if (idtvec_info & VMCS_IDT_VEC_VALID) {
|
|
switch (idtvec_info & VMCS_IDT_VEC_TYPE) {
|
|
case VMCS_IDT_VEC_HWINTR:
|
|
case VMCS_IDT_VEC_SWINTR:
|
|
env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;
|
|
break;
|
|
case VMCS_IDT_VEC_NMI:
|
|
env->nmi_injected = true;
|
|
break;
|
|
case VMCS_IDT_VEC_HWEXCEPTION:
|
|
case VMCS_IDT_VEC_SWEXCEPTION:
|
|
env->exception_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;
|
|
break;
|
|
case VMCS_IDT_VEC_PRIV_SWEXCEPTION:
|
|
default:
|
|
abort();
|
|
}
|
|
if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION ||
|
|
(idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) {
|
|
env->ins_len = ins_len;
|
|
}
|
|
if (idtvec_info & VMCS_INTR_DEL_ERRCODE) {
|
|
env->has_error_code = true;
|
|
env->error_code = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERROR);
|
|
}
|
|
}
|
|
if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
|
|
VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {
|
|
env->hflags2 |= HF2_NMI_MASK;
|
|
} else {
|
|
env->hflags2 &= ~HF2_NMI_MASK;
|
|
}
|
|
if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
|
|
(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
|
|
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
|
|
env->hflags |= HF_INHIBIT_IRQ_MASK;
|
|
} else {
|
|
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
|
|
}
|
|
}
|
|
|
|
int hvf_vcpu_exec(CPUState *cpu)
|
|
{
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
CPUX86State *env = &x86_cpu->env;
|
|
int ret = 0;
|
|
uint64_t rip = 0;
|
|
|
|
if (hvf_process_events(cpu)) {
|
|
return EXCP_HLT;
|
|
}
|
|
|
|
do {
|
|
if (cpu->vcpu_dirty) {
|
|
hvf_put_registers(cpu);
|
|
cpu->vcpu_dirty = false;
|
|
}
|
|
|
|
if (hvf_inject_interrupts(cpu)) {
|
|
return EXCP_INTERRUPT;
|
|
}
|
|
vmx_update_tpr(cpu);
|
|
|
|
qemu_mutex_unlock_iothread();
|
|
if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) {
|
|
qemu_mutex_lock_iothread();
|
|
return EXCP_HLT;
|
|
}
|
|
|
|
hv_return_t r = hv_vcpu_run(cpu->hvf_fd);
|
|
assert_hvf_ok(r);
|
|
|
|
/* handle VMEXIT */
|
|
uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON);
|
|
uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);
|
|
uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd,
|
|
VMCS_EXIT_INSTRUCTION_LENGTH);
|
|
|
|
uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
|
|
|
|
hvf_store_events(cpu, ins_len, idtvec_info);
|
|
rip = rreg(cpu->hvf_fd, HV_X86_RIP);
|
|
RFLAGS(env) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
|
|
env->eflags = RFLAGS(env);
|
|
|
|
qemu_mutex_lock_iothread();
|
|
|
|
update_apic_tpr(cpu);
|
|
current_cpu = cpu;
|
|
|
|
ret = 0;
|
|
switch (exit_reason) {
|
|
case EXIT_REASON_HLT: {
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(EFLAGS(env) & IF_MASK))
|
|
&& !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
|
|
!(idtvec_info & VMCS_IDT_VEC_VALID)) {
|
|
cpu->halted = 1;
|
|
ret = EXCP_HLT;
|
|
}
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
}
|
|
case EXIT_REASON_MWAIT: {
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
}
|
|
/* Need to check if MMIO or unmmaped fault */
|
|
case EXIT_REASON_EPT_FAULT:
|
|
{
|
|
hvf_slot *slot;
|
|
uint64_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
|
|
|
|
if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) &&
|
|
((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) {
|
|
vmx_set_nmi_blocking(cpu);
|
|
}
|
|
|
|
slot = hvf_find_overlap_slot(gpa, gpa);
|
|
/* mmio */
|
|
if (ept_emulation_fault(slot, gpa, exit_qual)) {
|
|
struct x86_decode decode;
|
|
|
|
load_regs(cpu);
|
|
env->hvf_emul->fetch_rip = rip;
|
|
|
|
decode_instruction(env, &decode);
|
|
exec_instruction(env, &decode);
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case EXIT_REASON_INOUT:
|
|
{
|
|
uint32_t in = (exit_qual & 8) != 0;
|
|
uint32_t size = (exit_qual & 7) + 1;
|
|
uint32_t string = (exit_qual & 16) != 0;
|
|
uint32_t port = exit_qual >> 16;
|
|
/*uint32_t rep = (exit_qual & 0x20) != 0;*/
|
|
|
|
if (!string && in) {
|
|
uint64_t val = 0;
|
|
load_regs(cpu);
|
|
hvf_handle_io(env, port, &val, 0, size, 1);
|
|
if (size == 1) {
|
|
AL(env) = val;
|
|
} else if (size == 2) {
|
|
AX(env) = val;
|
|
} else if (size == 4) {
|
|
RAX(env) = (uint32_t)val;
|
|
} else {
|
|
RAX(env) = (uint64_t)val;
|
|
}
|
|
RIP(env) += ins_len;
|
|
store_regs(cpu);
|
|
break;
|
|
} else if (!string && !in) {
|
|
RAX(env) = rreg(cpu->hvf_fd, HV_X86_RAX);
|
|
hvf_handle_io(env, port, &RAX(env), 1, size, 1);
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
struct x86_decode decode;
|
|
|
|
load_regs(cpu);
|
|
env->hvf_emul->fetch_rip = rip;
|
|
|
|
decode_instruction(env, &decode);
|
|
assert(ins_len == decode.len);
|
|
exec_instruction(env, &decode);
|
|
store_regs(cpu);
|
|
|
|
break;
|
|
}
|
|
case EXIT_REASON_CPUID: {
|
|
uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
|
|
uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX);
|
|
uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
|
|
uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
|
|
|
|
cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);
|
|
|
|
wreg(cpu->hvf_fd, HV_X86_RAX, rax);
|
|
wreg(cpu->hvf_fd, HV_X86_RBX, rbx);
|
|
wreg(cpu->hvf_fd, HV_X86_RCX, rcx);
|
|
wreg(cpu->hvf_fd, HV_X86_RDX, rdx);
|
|
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
case EXIT_REASON_XSETBV: {
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
CPUX86State *env = &x86_cpu->env;
|
|
uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
|
|
uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
|
|
uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
|
|
|
|
if (ecx) {
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
env->xcr0 = ((uint64_t)edx << 32) | eax;
|
|
wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1);
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
case EXIT_REASON_INTR_WINDOW:
|
|
vmx_clear_int_window_exiting(cpu);
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
case EXIT_REASON_NMI_WINDOW:
|
|
vmx_clear_nmi_window_exiting(cpu);
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
case EXIT_REASON_EXT_INTR:
|
|
/* force exit and allow io handling */
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
case EXIT_REASON_RDMSR:
|
|
case EXIT_REASON_WRMSR:
|
|
{
|
|
load_regs(cpu);
|
|
if (exit_reason == EXIT_REASON_RDMSR) {
|
|
simulate_rdmsr(cpu);
|
|
} else {
|
|
simulate_wrmsr(cpu);
|
|
}
|
|
RIP(env) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
case EXIT_REASON_CR_ACCESS: {
|
|
int cr;
|
|
int reg;
|
|
|
|
load_regs(cpu);
|
|
cr = exit_qual & 15;
|
|
reg = (exit_qual >> 8) & 15;
|
|
|
|
switch (cr) {
|
|
case 0x0: {
|
|
macvm_set_cr0(cpu->hvf_fd, RRX(env, reg));
|
|
break;
|
|
}
|
|
case 4: {
|
|
macvm_set_cr4(cpu->hvf_fd, RRX(env, reg));
|
|
break;
|
|
}
|
|
case 8: {
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
if (exit_qual & 0x10) {
|
|
RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
|
|
} else {
|
|
int tpr = RRX(env, reg);
|
|
cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
|
|
ret = EXCP_INTERRUPT;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
error_report("Unrecognized CR %d", cr);
|
|
abort();
|
|
}
|
|
RIP(env) += ins_len;
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
case EXIT_REASON_APIC_ACCESS: { /* TODO */
|
|
struct x86_decode decode;
|
|
|
|
load_regs(cpu);
|
|
env->hvf_emul->fetch_rip = rip;
|
|
|
|
decode_instruction(env, &decode);
|
|
exec_instruction(env, &decode);
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
case EXIT_REASON_TPR: {
|
|
ret = 1;
|
|
break;
|
|
}
|
|
case EXIT_REASON_TASK_SWITCH: {
|
|
uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
|
|
x68_segment_selector sel = {.sel = exit_qual & 0xffff};
|
|
vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
|
|
vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo
|
|
& VMCS_INTR_T_MASK);
|
|
break;
|
|
}
|
|
case EXIT_REASON_TRIPLE_FAULT: {
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
}
|
|
case EXIT_REASON_RDPMC:
|
|
wreg(cpu->hvf_fd, HV_X86_RAX, 0);
|
|
wreg(cpu->hvf_fd, HV_X86_RDX, 0);
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
case VMX_REASON_VMCALL:
|
|
env->exception_injected = EXCP0D_GPF;
|
|
env->has_error_code = true;
|
|
env->error_code = 0;
|
|
break;
|
|
default:
|
|
error_report("%llx: unhandled exit %llx", rip, exit_reason);
|
|
}
|
|
} while (ret == 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
bool hvf_allowed;
|
|
|
|
static int hvf_accel_init(MachineState *ms)
|
|
{
|
|
int x;
|
|
hv_return_t ret;
|
|
HVFState *s;
|
|
|
|
ret = hv_vm_create(HV_VM_DEFAULT);
|
|
assert_hvf_ok(ret);
|
|
|
|
s = g_new0(HVFState, 1);
|
|
|
|
s->num_slots = 32;
|
|
for (x = 0; x < s->num_slots; ++x) {
|
|
s->slots[x].size = 0;
|
|
s->slots[x].slot_id = x;
|
|
}
|
|
|
|
hvf_state = s;
|
|
cpu_interrupt_handler = hvf_handle_interrupt;
|
|
memory_listener_register(&hvf_memory_listener, &address_space_memory);
|
|
return 0;
|
|
}
|
|
|
|
static void hvf_accel_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AccelClass *ac = ACCEL_CLASS(oc);
|
|
ac->name = "HVF";
|
|
ac->init_machine = hvf_accel_init;
|
|
ac->allowed = &hvf_allowed;
|
|
}
|
|
|
|
static const TypeInfo hvf_accel_type = {
|
|
.name = TYPE_HVF_ACCEL,
|
|
.parent = TYPE_ACCEL,
|
|
.class_init = hvf_accel_class_init,
|
|
};
|
|
|
|
static void hvf_type_init(void)
|
|
{
|
|
type_register_static(&hvf_accel_type);
|
|
}
|
|
|
|
type_init(hvf_type_init);
|