The parsing of KVM_SET_LAPIC's input depends on the current value of the
APIC base MSR---which indeed is stored in APICCommonState---but for historical
reasons APIC base is set through KVM_SET_SREGS together with cr8 (which is
really just the APIC TPR) and the actual "special CPU registers".
APIC base must now be set before the actual LAPIC registers, so do that
in kvm_apic_put. It will be set again to the same value with KVM_SET_SREGS,
but that's not a big issue.
This only happens since Linux 4.8, which checks for x2apic mode in
KVM_SET_LAPIC. However it's really a QEMU bug; until the recent
commit 78d6a05
("x86/lapic: Load LAPIC state at post_load", 2016-09-13)
QEMU was indeed setting APIC base (via KVM_SET_SREGS) before the other
LAPIC registers.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
251 lines
6.8 KiB
C
251 lines
6.8 KiB
C
/*
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* KVM in-kernel APIC support
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*
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* Copyright (c) 2011 Siemens AG
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*
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* Authors:
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* Jan Kiszka <jan.kiszka@siemens.com>
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*
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* This work is licensed under the terms of the GNU GPL version 2.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/i386/apic_internal.h"
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#include "hw/pci/msi.h"
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#include "sysemu/kvm.h"
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#include "target-i386/kvm_i386.h"
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static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
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int reg_id, uint32_t val)
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{
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*((uint32_t *)(kapic->regs + (reg_id << 4))) = val;
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}
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static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,
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int reg_id)
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{
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return *((uint32_t *)(kapic->regs + (reg_id << 4)));
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}
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static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic)
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{
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int i;
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memset(kapic, 0, sizeof(*kapic));
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kvm_apic_set_reg(kapic, 0x2, s->id << 24);
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kvm_apic_set_reg(kapic, 0x8, s->tpr);
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kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);
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kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
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kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);
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for (i = 0; i < 8; i++) {
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kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);
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kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);
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kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);
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}
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kvm_apic_set_reg(kapic, 0x28, s->esr);
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kvm_apic_set_reg(kapic, 0x30, s->icr[0]);
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kvm_apic_set_reg(kapic, 0x31, s->icr[1]);
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for (i = 0; i < APIC_LVT_NB; i++) {
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kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);
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}
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kvm_apic_set_reg(kapic, 0x38, s->initial_count);
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kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);
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}
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void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
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{
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APICCommonState *s = APIC_COMMON(dev);
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int i, v;
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s->id = kvm_apic_get_reg(kapic, 0x2) >> 24;
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s->tpr = kvm_apic_get_reg(kapic, 0x8);
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s->arb_id = kvm_apic_get_reg(kapic, 0x9);
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s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24;
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s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28;
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s->spurious_vec = kvm_apic_get_reg(kapic, 0xf);
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for (i = 0; i < 8; i++) {
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s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i);
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s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i);
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s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i);
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}
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s->esr = kvm_apic_get_reg(kapic, 0x28);
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s->icr[0] = kvm_apic_get_reg(kapic, 0x30);
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s->icr[1] = kvm_apic_get_reg(kapic, 0x31);
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for (i = 0; i < APIC_LVT_NB; i++) {
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s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i);
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}
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s->initial_count = kvm_apic_get_reg(kapic, 0x38);
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s->divide_conf = kvm_apic_get_reg(kapic, 0x3e);
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v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
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s->count_shift = (v + 1) & 7;
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s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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apic_next_timer(s, s->initial_count_load_time);
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}
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static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
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{
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s->apicbase = val;
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}
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static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
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{
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s->tpr = (val & 0x0f) << 4;
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}
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static uint8_t kvm_apic_get_tpr(APICCommonState *s)
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{
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return s->tpr >> 4;
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}
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static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
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{
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struct kvm_tpr_access_ctl ctl = {
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.enabled = enable
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};
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kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl);
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}
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static void kvm_apic_vapic_base_update(APICCommonState *s)
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{
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struct kvm_vapic_addr vapid_addr = {
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.vapic_addr = s->vapic_paddr,
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};
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int ret;
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ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr);
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if (ret < 0) {
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fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
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strerror(-ret));
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abort();
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}
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}
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static void kvm_apic_put(void *data)
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{
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APICCommonState *s = data;
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struct kvm_lapic_state kapic;
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int ret;
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kvm_put_apicbase(s->cpu, s->apicbase);
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kvm_put_apic_state(s, &kapic);
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ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic);
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if (ret < 0) {
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fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(ret));
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abort();
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}
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}
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static void kvm_apic_post_load(APICCommonState *s)
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{
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run_on_cpu(CPU(s->cpu), kvm_apic_put, s);
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}
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static void do_inject_external_nmi(void *data)
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{
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APICCommonState *s = data;
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CPUState *cpu = CPU(s->cpu);
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uint32_t lvt;
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int ret;
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cpu_synchronize_state(cpu);
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lvt = s->lvt[APIC_LVT_LINT1];
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if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
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ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
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if (ret < 0) {
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fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
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strerror(-ret));
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}
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}
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}
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static void kvm_apic_external_nmi(APICCommonState *s)
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{
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run_on_cpu(CPU(s->cpu), do_inject_external_nmi, s);
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}
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static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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return ~(uint64_t)0;
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}
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static void kvm_apic_mem_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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MSIMessage msg = { .address = addr, .data = data };
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int ret;
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ret = kvm_irqchip_send_msi(kvm_state, msg);
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if (ret < 0) {
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fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n",
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strerror(-ret));
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}
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}
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static const MemoryRegionOps kvm_apic_io_ops = {
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.read = kvm_apic_mem_read,
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.write = kvm_apic_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void kvm_apic_reset(APICCommonState *s)
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{
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/* Not used by KVM, which uses the CPU mp_state instead. */
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s->wait_for_sipi = 0;
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run_on_cpu(CPU(s->cpu), kvm_apic_put, s);
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}
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static void kvm_apic_realize(DeviceState *dev, Error **errp)
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{
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APICCommonState *s = APIC_COMMON(dev);
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memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s,
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"kvm-apic-msi", APIC_SPACE_SIZE);
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if (kvm_has_gsi_routing()) {
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msi_nonbroken = true;
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}
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}
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static void kvm_apic_unrealize(DeviceState *dev, Error **errp)
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{
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}
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static void kvm_apic_class_init(ObjectClass *klass, void *data)
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{
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APICCommonClass *k = APIC_COMMON_CLASS(klass);
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k->realize = kvm_apic_realize;
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k->unrealize = kvm_apic_unrealize;
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k->reset = kvm_apic_reset;
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k->set_base = kvm_apic_set_base;
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k->set_tpr = kvm_apic_set_tpr;
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k->get_tpr = kvm_apic_get_tpr;
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k->post_load = kvm_apic_post_load;
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k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting;
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k->vapic_base_update = kvm_apic_vapic_base_update;
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k->external_nmi = kvm_apic_external_nmi;
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}
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static const TypeInfo kvm_apic_info = {
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.name = "kvm-apic",
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.parent = TYPE_APIC_COMMON,
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.instance_size = sizeof(APICCommonState),
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.class_init = kvm_apic_class_init,
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};
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static void kvm_apic_register_types(void)
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{
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type_register_static(&kvm_apic_info);
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}
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type_init(kvm_apic_register_types)
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