With Apple Silicon available to the masses, it's a good time to add support for driving its virtualization extensions from QEMU. This patch adds all necessary architecture specific code to get basic VMs working, including save/restore. Known limitations: - WFI handling is missing (follows in later patch) - No watchpoint/breakpoint support Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Sergio Lopez <slp@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20210916155404.86958-5-agraf@csgraf.de [PMM: added missing #include] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
674 lines
21 KiB
C
674 lines
21 KiB
C
/* Copyright 2008 IBM Corporation
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* 2008 Red Hat, Inc.
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* Copyright 2011 Intel Corporation
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* Copyright 2016 Veertu, Inc.
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* Copyright 2017 The Android Open Source Project
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*
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* QEMU Hypervisor.framework support
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* This file contain code under public domain from the hvdos project:
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* https://github.com/mist64/hvdos
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*
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* Parts Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "sysemu/hvf.h"
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#include "sysemu/hvf_int.h"
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#include "sysemu/runstate.h"
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#include "sysemu/cpus.h"
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#include "hvf-i386.h"
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#include "vmcs.h"
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#include "vmx.h"
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#include "x86.h"
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#include "x86_descr.h"
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#include "x86_mmu.h"
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#include "x86_decode.h"
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#include "x86_emu.h"
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#include "x86_task.h"
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#include "x86hvf.h"
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#include <Hypervisor/hv.h>
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#include <Hypervisor/hv_vmx.h>
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#include <sys/sysctl.h>
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#include "hw/i386/apic_internal.h"
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#include "qemu/main-loop.h"
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#include "qemu/accel.h"
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#include "target/i386/cpu.h"
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void vmx_update_tpr(CPUState *cpu)
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{
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/* TODO: need integrate APIC handling */
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X86CPU *x86_cpu = X86_CPU(cpu);
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int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
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int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
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wreg(cpu->hvf->fd, HV_X86_TPR, tpr);
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if (irr == -1) {
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wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);
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} else {
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wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :
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irr >> 4);
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}
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}
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static void update_apic_tpr(CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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int tpr = rreg(cpu->hvf->fd, HV_X86_TPR) >> 4;
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cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
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}
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#define VECTORING_INFO_VECTOR_MASK 0xff
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void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer,
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int direction, int size, int count)
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{
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int i;
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uint8_t *ptr = buffer;
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for (i = 0; i < count; i++) {
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address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED,
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ptr, size,
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direction);
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ptr += size;
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}
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}
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static bool ept_emulation_fault(hvf_slot *slot, uint64_t gpa, uint64_t ept_qual)
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{
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int read, write;
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/* EPT fault on an instruction fetch doesn't make sense here */
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if (ept_qual & EPT_VIOLATION_INST_FETCH) {
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return false;
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}
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/* EPT fault must be a read fault or a write fault */
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read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
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write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
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if ((read | write) == 0) {
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return false;
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}
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if (write && slot) {
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if (slot->flags & HVF_SLOT_LOG) {
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memory_region_set_dirty(slot->region, gpa - slot->start, 1);
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hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
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HV_MEMORY_READ | HV_MEMORY_WRITE);
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}
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}
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/*
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* The EPT violation must have been caused by accessing a
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* guest-physical address that is a translation of a guest-linear
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* address.
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*/
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if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
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(ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
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return false;
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}
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if (!slot) {
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return true;
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}
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if (!memory_region_is_ram(slot->region) &&
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!(read && memory_region_is_romd(slot->region))) {
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return true;
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}
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return false;
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}
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void hvf_arch_vcpu_destroy(CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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g_free(env->hvf_mmio_buf);
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}
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static void init_tsc_freq(CPUX86State *env)
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{
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size_t length;
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uint64_t tsc_freq;
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if (env->tsc_khz != 0) {
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return;
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}
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length = sizeof(uint64_t);
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if (sysctlbyname("machdep.tsc.frequency", &tsc_freq, &length, NULL, 0)) {
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return;
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}
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env->tsc_khz = tsc_freq / 1000; /* Hz to KHz */
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}
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static void init_apic_bus_freq(CPUX86State *env)
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{
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size_t length;
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uint64_t bus_freq;
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if (env->apic_bus_freq != 0) {
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return;
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}
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length = sizeof(uint64_t);
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if (sysctlbyname("hw.busfrequency", &bus_freq, &length, NULL, 0)) {
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return;
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}
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env->apic_bus_freq = bus_freq;
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}
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static inline bool tsc_is_known(CPUX86State *env)
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{
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return env->tsc_khz != 0;
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}
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static inline bool apic_bus_freq_is_known(CPUX86State *env)
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{
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return env->apic_bus_freq != 0;
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}
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void hvf_kick_vcpu_thread(CPUState *cpu)
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{
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cpus_kick_thread(cpu);
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}
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int hvf_arch_init(void)
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{
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return 0;
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}
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int hvf_arch_init_vcpu(CPUState *cpu)
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{
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X86CPU *x86cpu = X86_CPU(cpu);
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CPUX86State *env = &x86cpu->env;
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init_emu();
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init_decoder();
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hvf_state->hvf_caps = g_new0(struct hvf_vcpu_caps, 1);
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env->hvf_mmio_buf = g_new(char, 4096);
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if (x86cpu->vmware_cpuid_freq) {
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init_tsc_freq(env);
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init_apic_bus_freq(env);
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if (!tsc_is_known(env) || !apic_bus_freq_is_known(env)) {
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error_report("vmware-cpuid-freq: feature couldn't be enabled");
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}
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}
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if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED,
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&hvf_state->hvf_caps->vmx_cap_pinbased)) {
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abort();
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}
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if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED,
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&hvf_state->hvf_caps->vmx_cap_procbased)) {
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abort();
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}
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if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2,
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&hvf_state->hvf_caps->vmx_cap_procbased2)) {
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abort();
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}
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if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY,
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&hvf_state->hvf_caps->vmx_cap_entry)) {
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abort();
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}
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/* set VMCS control fields */
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wvmcs(cpu->hvf->fd, VMCS_PIN_BASED_CTLS,
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cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased,
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VMCS_PIN_BASED_CTLS_EXTINT |
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VMCS_PIN_BASED_CTLS_NMI |
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VMCS_PIN_BASED_CTLS_VNMI));
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wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS,
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cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
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VMCS_PRI_PROC_BASED_CTLS_HLT |
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VMCS_PRI_PROC_BASED_CTLS_MWAIT |
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VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
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VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
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VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
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wvmcs(cpu->hvf->fd, VMCS_SEC_PROC_BASED_CTLS,
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cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,
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VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
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wvmcs(cpu->hvf->fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
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0));
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wvmcs(cpu->hvf->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
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wvmcs(cpu->hvf->fd, VMCS_TPR_THRESHOLD, 0);
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x86cpu = X86_CPU(cpu);
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x86cpu->env.xsave_buf_len = 4096;
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x86cpu->env.xsave_buf = qemu_memalign(4096, x86cpu->env.xsave_buf_len);
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/*
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* The allocated storage must be large enough for all of the
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* possible XSAVE state components.
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*/
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assert(hvf_get_supported_cpuid(0xd, 0, R_ECX) <= x86cpu->env.xsave_buf_len);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_STAR, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_LSTAR, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_CSTAR, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FMASK, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_FSBASE, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_GSBASE, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_KERNELGSBASE, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_TSC_AUX, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_TSC, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_CS, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_EIP, 1);
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hv_vcpu_enable_native_msr(cpu->hvf->fd, MSR_IA32_SYSENTER_ESP, 1);
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return 0;
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}
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static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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env->exception_nr = -1;
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env->exception_pending = 0;
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env->exception_injected = 0;
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env->interrupt_injected = -1;
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env->nmi_injected = false;
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env->ins_len = 0;
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env->has_error_code = false;
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if (idtvec_info & VMCS_IDT_VEC_VALID) {
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switch (idtvec_info & VMCS_IDT_VEC_TYPE) {
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case VMCS_IDT_VEC_HWINTR:
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case VMCS_IDT_VEC_SWINTR:
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env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;
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break;
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case VMCS_IDT_VEC_NMI:
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env->nmi_injected = true;
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break;
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case VMCS_IDT_VEC_HWEXCEPTION:
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case VMCS_IDT_VEC_SWEXCEPTION:
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env->exception_nr = idtvec_info & VMCS_IDT_VEC_VECNUM;
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env->exception_injected = 1;
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break;
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case VMCS_IDT_VEC_PRIV_SWEXCEPTION:
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default:
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abort();
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}
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if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION ||
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(idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) {
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env->ins_len = ins_len;
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}
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if (idtvec_info & VMCS_IDT_VEC_ERRCODE_VALID) {
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env->has_error_code = true;
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env->error_code = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_ERROR);
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}
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}
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if ((rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &
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VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {
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env->hflags2 |= HF2_NMI_MASK;
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} else {
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env->hflags2 &= ~HF2_NMI_MASK;
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}
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if (rvmcs(cpu->hvf->fd, VMCS_GUEST_INTERRUPTIBILITY) &
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(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
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VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
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env->hflags |= HF_INHIBIT_IRQ_MASK;
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} else {
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env->hflags &= ~HF_INHIBIT_IRQ_MASK;
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}
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}
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static void hvf_cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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/*
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* A wrapper extends cpu_x86_cpuid with 0x40000000 and 0x40000010 leafs,
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* leafs 0x40000001-0x4000000F are filled with zeros
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* Provides vmware-cpuid-freq support to hvf
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*
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* Note: leaf 0x40000000 not exposes HVF,
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* leaving hypervisor signature empty
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*/
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if (index < 0x40000000 || index > 0x40000010 ||
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!tsc_is_known(env) || !apic_bus_freq_is_known(env)) {
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cpu_x86_cpuid(env, index, count, eax, ebx, ecx, edx);
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return;
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}
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switch (index) {
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case 0x40000000:
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*eax = 0x40000010; /* Max available cpuid leaf */
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*ebx = 0; /* Leave signature empty */
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*ecx = 0;
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*edx = 0;
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break;
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case 0x40000010:
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*eax = env->tsc_khz;
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*ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
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*ecx = 0;
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*edx = 0;
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break;
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default:
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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}
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}
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int hvf_vcpu_exec(CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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CPUX86State *env = &x86_cpu->env;
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int ret = 0;
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uint64_t rip = 0;
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if (hvf_process_events(cpu)) {
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return EXCP_HLT;
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}
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do {
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if (cpu->vcpu_dirty) {
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hvf_put_registers(cpu);
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cpu->vcpu_dirty = false;
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}
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if (hvf_inject_interrupts(cpu)) {
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return EXCP_INTERRUPT;
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}
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vmx_update_tpr(cpu);
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qemu_mutex_unlock_iothread();
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if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) {
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qemu_mutex_lock_iothread();
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return EXCP_HLT;
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}
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hv_return_t r = hv_vcpu_run(cpu->hvf->fd);
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assert_hvf_ok(r);
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/* handle VMEXIT */
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uint64_t exit_reason = rvmcs(cpu->hvf->fd, VMCS_EXIT_REASON);
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uint64_t exit_qual = rvmcs(cpu->hvf->fd, VMCS_EXIT_QUALIFICATION);
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uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf->fd,
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VMCS_EXIT_INSTRUCTION_LENGTH);
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uint64_t idtvec_info = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);
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hvf_store_events(cpu, ins_len, idtvec_info);
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rip = rreg(cpu->hvf->fd, HV_X86_RIP);
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env->eflags = rreg(cpu->hvf->fd, HV_X86_RFLAGS);
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qemu_mutex_lock_iothread();
|
|
|
|
update_apic_tpr(cpu);
|
|
current_cpu = cpu;
|
|
|
|
ret = 0;
|
|
switch (exit_reason) {
|
|
case EXIT_REASON_HLT: {
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(env->eflags & IF_MASK))
|
|
&& !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
|
|
!(idtvec_info & VMCS_IDT_VEC_VALID)) {
|
|
cpu->halted = 1;
|
|
ret = EXCP_HLT;
|
|
break;
|
|
}
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
}
|
|
case EXIT_REASON_MWAIT: {
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
}
|
|
/* Need to check if MMIO or unmapped fault */
|
|
case EXIT_REASON_EPT_FAULT:
|
|
{
|
|
hvf_slot *slot;
|
|
uint64_t gpa = rvmcs(cpu->hvf->fd, VMCS_GUEST_PHYSICAL_ADDRESS);
|
|
|
|
if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) &&
|
|
((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) {
|
|
vmx_set_nmi_blocking(cpu);
|
|
}
|
|
|
|
slot = hvf_find_overlap_slot(gpa, 1);
|
|
/* mmio */
|
|
if (ept_emulation_fault(slot, gpa, exit_qual)) {
|
|
struct x86_decode decode;
|
|
|
|
load_regs(cpu);
|
|
decode_instruction(env, &decode);
|
|
exec_instruction(env, &decode);
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case EXIT_REASON_INOUT:
|
|
{
|
|
uint32_t in = (exit_qual & 8) != 0;
|
|
uint32_t size = (exit_qual & 7) + 1;
|
|
uint32_t string = (exit_qual & 16) != 0;
|
|
uint32_t port = exit_qual >> 16;
|
|
/*uint32_t rep = (exit_qual & 0x20) != 0;*/
|
|
|
|
if (!string && in) {
|
|
uint64_t val = 0;
|
|
load_regs(cpu);
|
|
hvf_handle_io(env, port, &val, 0, size, 1);
|
|
if (size == 1) {
|
|
AL(env) = val;
|
|
} else if (size == 2) {
|
|
AX(env) = val;
|
|
} else if (size == 4) {
|
|
RAX(env) = (uint32_t)val;
|
|
} else {
|
|
RAX(env) = (uint64_t)val;
|
|
}
|
|
env->eip += ins_len;
|
|
store_regs(cpu);
|
|
break;
|
|
} else if (!string && !in) {
|
|
RAX(env) = rreg(cpu->hvf->fd, HV_X86_RAX);
|
|
hvf_handle_io(env, port, &RAX(env), 1, size, 1);
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
struct x86_decode decode;
|
|
|
|
load_regs(cpu);
|
|
decode_instruction(env, &decode);
|
|
assert(ins_len == decode.len);
|
|
exec_instruction(env, &decode);
|
|
store_regs(cpu);
|
|
|
|
break;
|
|
}
|
|
case EXIT_REASON_CPUID: {
|
|
uint32_t rax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);
|
|
uint32_t rbx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RBX);
|
|
uint32_t rcx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);
|
|
uint32_t rdx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);
|
|
|
|
if (rax == 1) {
|
|
/* CPUID1.ecx.OSXSAVE needs to know CR4 */
|
|
env->cr[4] = rvmcs(cpu->hvf->fd, VMCS_GUEST_CR4);
|
|
}
|
|
hvf_cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);
|
|
|
|
wreg(cpu->hvf->fd, HV_X86_RAX, rax);
|
|
wreg(cpu->hvf->fd, HV_X86_RBX, rbx);
|
|
wreg(cpu->hvf->fd, HV_X86_RCX, rcx);
|
|
wreg(cpu->hvf->fd, HV_X86_RDX, rdx);
|
|
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
case EXIT_REASON_XSETBV: {
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
CPUX86State *env = &x86_cpu->env;
|
|
uint32_t eax = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RAX);
|
|
uint32_t ecx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RCX);
|
|
uint32_t edx = (uint32_t)rreg(cpu->hvf->fd, HV_X86_RDX);
|
|
|
|
if (ecx) {
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
env->xcr0 = ((uint64_t)edx << 32) | eax;
|
|
wreg(cpu->hvf->fd, HV_X86_XCR0, env->xcr0 | 1);
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
}
|
|
case EXIT_REASON_INTR_WINDOW:
|
|
vmx_clear_int_window_exiting(cpu);
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
case EXIT_REASON_NMI_WINDOW:
|
|
vmx_clear_nmi_window_exiting(cpu);
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
case EXIT_REASON_EXT_INTR:
|
|
/* force exit and allow io handling */
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
case EXIT_REASON_RDMSR:
|
|
case EXIT_REASON_WRMSR:
|
|
{
|
|
load_regs(cpu);
|
|
if (exit_reason == EXIT_REASON_RDMSR) {
|
|
simulate_rdmsr(cpu);
|
|
} else {
|
|
simulate_wrmsr(cpu);
|
|
}
|
|
env->eip += ins_len;
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
case EXIT_REASON_CR_ACCESS: {
|
|
int cr;
|
|
int reg;
|
|
|
|
load_regs(cpu);
|
|
cr = exit_qual & 15;
|
|
reg = (exit_qual >> 8) & 15;
|
|
|
|
switch (cr) {
|
|
case 0x0: {
|
|
macvm_set_cr0(cpu->hvf->fd, RRX(env, reg));
|
|
break;
|
|
}
|
|
case 4: {
|
|
macvm_set_cr4(cpu->hvf->fd, RRX(env, reg));
|
|
break;
|
|
}
|
|
case 8: {
|
|
X86CPU *x86_cpu = X86_CPU(cpu);
|
|
if (exit_qual & 0x10) {
|
|
RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
|
|
} else {
|
|
int tpr = RRX(env, reg);
|
|
cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
|
|
ret = EXCP_INTERRUPT;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
error_report("Unrecognized CR %d", cr);
|
|
abort();
|
|
}
|
|
env->eip += ins_len;
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
case EXIT_REASON_APIC_ACCESS: { /* TODO */
|
|
struct x86_decode decode;
|
|
|
|
load_regs(cpu);
|
|
decode_instruction(env, &decode);
|
|
exec_instruction(env, &decode);
|
|
store_regs(cpu);
|
|
break;
|
|
}
|
|
case EXIT_REASON_TPR: {
|
|
ret = 1;
|
|
break;
|
|
}
|
|
case EXIT_REASON_TASK_SWITCH: {
|
|
uint64_t vinfo = rvmcs(cpu->hvf->fd, VMCS_IDT_VECTORING_INFO);
|
|
x68_segment_selector sel = {.sel = exit_qual & 0xffff};
|
|
vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
|
|
vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo
|
|
& VMCS_INTR_T_MASK);
|
|
break;
|
|
}
|
|
case EXIT_REASON_TRIPLE_FAULT: {
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
ret = EXCP_INTERRUPT;
|
|
break;
|
|
}
|
|
case EXIT_REASON_RDPMC:
|
|
wreg(cpu->hvf->fd, HV_X86_RAX, 0);
|
|
wreg(cpu->hvf->fd, HV_X86_RDX, 0);
|
|
macvm_set_rip(cpu, rip + ins_len);
|
|
break;
|
|
case VMX_REASON_VMCALL:
|
|
env->exception_nr = EXCP0D_GPF;
|
|
env->exception_injected = 1;
|
|
env->has_error_code = true;
|
|
env->error_code = 0;
|
|
break;
|
|
default:
|
|
error_report("%llx: unhandled exit %llx", rip, exit_reason);
|
|
}
|
|
} while (ret == 0);
|
|
|
|
return ret;
|
|
}
|