Add a virtual PMU device for virt machine while use PPI 7 for PMU overflow interrupt number. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1465267577-1808-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
973 lines
27 KiB
C
973 lines
27 KiB
C
/*
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* ARM implementation of KVM hooks, 64 bit specific code
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*
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* Copyright Mian-M. Hamayun 2013, Virtual Open Systems
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* Copyright Alex Bennée 2014, Linaro
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <sys/ptrace.h>
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#include <linux/elf.h>
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#include <linux/kvm.h>
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#include "qemu-common.h"
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#include "cpu.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "qemu/host-utils.h"
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#include "exec/gdbstub.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "internals.h"
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#include "hw/arm/arm.h"
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static bool have_guest_debug;
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/*
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* Although the ARM implementation of hardware assisted debugging
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* allows for different breakpoints per-core, the current GDB
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* interface treats them as a global pool of registers (which seems to
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* be the case for x86, ppc and s390). As a result we store one copy
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* of registers which is used for all active cores.
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*
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* Write access is serialised by virtue of the GDB protocol which
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* updates things. Read access (i.e. when the values are copied to the
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* vCPU) is also gated by GDB's run control.
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*
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* This is not unreasonable as most of the time debugging kernels you
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* never know which core will eventually execute your function.
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*/
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typedef struct {
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uint64_t bcr;
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uint64_t bvr;
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} HWBreakpoint;
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/* The watchpoint registers can cover more area than the requested
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* watchpoint so we need to store the additional information
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* somewhere. We also need to supply a CPUWatchpoint to the GDB stub
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* when the watchpoint is hit.
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*/
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typedef struct {
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uint64_t wcr;
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uint64_t wvr;
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CPUWatchpoint details;
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} HWWatchpoint;
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/* Maximum and current break/watch point counts */
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int max_hw_bps, max_hw_wps;
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GArray *hw_breakpoints, *hw_watchpoints;
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#define cur_hw_wps (hw_watchpoints->len)
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#define cur_hw_bps (hw_breakpoints->len)
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#define get_hw_bp(i) (&g_array_index(hw_breakpoints, HWBreakpoint, i))
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#define get_hw_wp(i) (&g_array_index(hw_watchpoints, HWWatchpoint, i))
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/**
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* kvm_arm_init_debug() - check for guest debug capabilities
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* @cs: CPUState
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*
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* kvm_check_extension returns the number of debug registers we have
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* or 0 if we have none.
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*
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*/
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static void kvm_arm_init_debug(CPUState *cs)
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{
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have_guest_debug = kvm_check_extension(cs->kvm_state,
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KVM_CAP_SET_GUEST_DEBUG);
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max_hw_wps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_WPS);
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hw_watchpoints = g_array_sized_new(true, true,
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sizeof(HWWatchpoint), max_hw_wps);
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max_hw_bps = kvm_check_extension(cs->kvm_state, KVM_CAP_GUEST_DEBUG_HW_BPS);
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hw_breakpoints = g_array_sized_new(true, true,
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sizeof(HWBreakpoint), max_hw_bps);
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return;
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}
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/**
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* insert_hw_breakpoint()
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* @addr: address of breakpoint
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*
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* See ARM ARM D2.9.1 for details but here we are only going to create
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* simple un-linked breakpoints (i.e. we don't chain breakpoints
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* together to match address and context or vmid). The hardware is
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* capable of fancier matching but that will require exposing that
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* fanciness to GDB's interface
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*
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* D7.3.2 DBGBCR<n>_EL1, Debug Breakpoint Control Registers
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*
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* 31 24 23 20 19 16 15 14 13 12 9 8 5 4 3 2 1 0
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* +------+------+-------+-----+----+------+-----+------+-----+---+
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* | RES0 | BT | LBN | SSC | HMC| RES0 | BAS | RES0 | PMC | E |
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* +------+------+-------+-----+----+------+-----+------+-----+---+
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*
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* BT: Breakpoint type (0 = unlinked address match)
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* LBN: Linked BP number (0 = unused)
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* SSC/HMC/PMC: Security, Higher and Priv access control (Table D-12)
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* BAS: Byte Address Select (RES1 for AArch64)
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* E: Enable bit
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*/
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static int insert_hw_breakpoint(target_ulong addr)
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{
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HWBreakpoint brk = {
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.bcr = 0x1, /* BCR E=1, enable */
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.bvr = addr
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};
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if (cur_hw_bps >= max_hw_bps) {
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return -ENOBUFS;
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}
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brk.bcr = deposit32(brk.bcr, 1, 2, 0x3); /* PMC = 11 */
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brk.bcr = deposit32(brk.bcr, 5, 4, 0xf); /* BAS = RES1 */
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g_array_append_val(hw_breakpoints, brk);
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return 0;
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}
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/**
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* delete_hw_breakpoint()
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* @pc: address of breakpoint
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*
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* Delete a breakpoint and shuffle any above down
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*/
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static int delete_hw_breakpoint(target_ulong pc)
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{
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int i;
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for (i = 0; i < hw_breakpoints->len; i++) {
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HWBreakpoint *brk = get_hw_bp(i);
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if (brk->bvr == pc) {
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g_array_remove_index(hw_breakpoints, i);
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return 0;
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}
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}
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return -ENOENT;
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}
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/**
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* insert_hw_watchpoint()
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* @addr: address of watch point
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* @len: size of area
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* @type: type of watch point
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*
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* See ARM ARM D2.10. As with the breakpoints we can do some advanced
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* stuff if we want to. The watch points can be linked with the break
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* points above to make them context aware. However for simplicity
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* currently we only deal with simple read/write watch points.
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*
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* D7.3.11 DBGWCR<n>_EL1, Debug Watchpoint Control Registers
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*
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* 31 29 28 24 23 21 20 19 16 15 14 13 12 5 4 3 2 1 0
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* +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
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* | RES0 | MASK | RES0 | WT | LBN | SSC | HMC | BAS | LSC | PAC | E |
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* +------+-------+------+----+-----+-----+-----+-----+-----+-----+---+
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*
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* MASK: num bits addr mask (0=none,01/10=res,11=3 bits (8 bytes))
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* WT: 0 - unlinked, 1 - linked (not currently used)
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* LBN: Linked BP number (not currently used)
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* SSC/HMC/PAC: Security, Higher and Priv access control (Table D2-11)
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* BAS: Byte Address Select
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* LSC: Load/Store control (01: load, 10: store, 11: both)
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* E: Enable
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*
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* The bottom 2 bits of the value register are masked. Therefore to
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* break on any sizes smaller than an unaligned word you need to set
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* MASK=0, BAS=bit per byte in question. For larger regions (^2) you
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* need to ensure you mask the address as required and set BAS=0xff
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*/
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static int insert_hw_watchpoint(target_ulong addr,
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target_ulong len, int type)
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{
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HWWatchpoint wp = {
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.wcr = 1, /* E=1, enable */
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.wvr = addr & (~0x7ULL),
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.details = { .vaddr = addr, .len = len }
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};
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if (cur_hw_wps >= max_hw_wps) {
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return -ENOBUFS;
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}
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/*
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* HMC=0 SSC=0 PAC=3 will hit EL0 or EL1, any security state,
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* valid whether EL3 is implemented or not
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*/
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wp.wcr = deposit32(wp.wcr, 1, 2, 3);
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switch (type) {
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case GDB_WATCHPOINT_READ:
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wp.wcr = deposit32(wp.wcr, 3, 2, 1);
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wp.details.flags = BP_MEM_READ;
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break;
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case GDB_WATCHPOINT_WRITE:
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wp.wcr = deposit32(wp.wcr, 3, 2, 2);
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wp.details.flags = BP_MEM_WRITE;
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break;
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case GDB_WATCHPOINT_ACCESS:
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wp.wcr = deposit32(wp.wcr, 3, 2, 3);
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wp.details.flags = BP_MEM_ACCESS;
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break;
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default:
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g_assert_not_reached();
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break;
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}
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if (len <= 8) {
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/* we align the address and set the bits in BAS */
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int off = addr & 0x7;
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int bas = (1 << len) - 1;
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wp.wcr = deposit32(wp.wcr, 5 + off, 8 - off, bas);
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} else {
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/* For ranges above 8 bytes we need to be a power of 2 */
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if (is_power_of_2(len)) {
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int bits = ctz64(len);
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wp.wvr &= ~((1 << bits) - 1);
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wp.wcr = deposit32(wp.wcr, 24, 4, bits);
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wp.wcr = deposit32(wp.wcr, 5, 8, 0xff);
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} else {
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return -ENOBUFS;
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}
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}
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g_array_append_val(hw_watchpoints, wp);
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return 0;
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}
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static bool check_watchpoint_in_range(int i, target_ulong addr)
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{
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HWWatchpoint *wp = get_hw_wp(i);
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uint64_t addr_top, addr_bottom = wp->wvr;
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int bas = extract32(wp->wcr, 5, 8);
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int mask = extract32(wp->wcr, 24, 4);
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if (mask) {
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addr_top = addr_bottom + (1 << mask);
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} else {
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/* BAS must be contiguous but can offset against the base
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* address in DBGWVR */
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addr_bottom = addr_bottom + ctz32(bas);
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addr_top = addr_bottom + clo32(bas);
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}
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if (addr >= addr_bottom && addr <= addr_top) {
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return true;
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}
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return false;
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}
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/**
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* delete_hw_watchpoint()
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* @addr: address of breakpoint
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*
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* Delete a breakpoint and shuffle any above down
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*/
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static int delete_hw_watchpoint(target_ulong addr,
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target_ulong len, int type)
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{
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int i;
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for (i = 0; i < cur_hw_wps; i++) {
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if (check_watchpoint_in_range(i, addr)) {
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g_array_remove_index(hw_watchpoints, i);
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return 0;
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}
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}
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return -ENOENT;
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}
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int kvm_arch_insert_hw_breakpoint(target_ulong addr,
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target_ulong len, int type)
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{
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switch (type) {
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case GDB_BREAKPOINT_HW:
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return insert_hw_breakpoint(addr);
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break;
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case GDB_WATCHPOINT_READ:
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case GDB_WATCHPOINT_WRITE:
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case GDB_WATCHPOINT_ACCESS:
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return insert_hw_watchpoint(addr, len, type);
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default:
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return -ENOSYS;
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}
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}
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int kvm_arch_remove_hw_breakpoint(target_ulong addr,
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target_ulong len, int type)
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{
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switch (type) {
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case GDB_BREAKPOINT_HW:
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return delete_hw_breakpoint(addr);
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break;
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case GDB_WATCHPOINT_READ:
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case GDB_WATCHPOINT_WRITE:
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case GDB_WATCHPOINT_ACCESS:
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return delete_hw_watchpoint(addr, len, type);
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default:
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return -ENOSYS;
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}
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}
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void kvm_arch_remove_all_hw_breakpoints(void)
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{
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if (cur_hw_wps > 0) {
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g_array_remove_range(hw_watchpoints, 0, cur_hw_wps);
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}
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if (cur_hw_bps > 0) {
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g_array_remove_range(hw_breakpoints, 0, cur_hw_bps);
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}
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}
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void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
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{
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int i;
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memset(ptr, 0, sizeof(struct kvm_guest_debug_arch));
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for (i = 0; i < max_hw_wps; i++) {
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HWWatchpoint *wp = get_hw_wp(i);
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ptr->dbg_wcr[i] = wp->wcr;
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ptr->dbg_wvr[i] = wp->wvr;
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}
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for (i = 0; i < max_hw_bps; i++) {
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HWBreakpoint *bp = get_hw_bp(i);
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ptr->dbg_bcr[i] = bp->bcr;
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ptr->dbg_bvr[i] = bp->bvr;
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}
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}
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bool kvm_arm_hw_debug_active(CPUState *cs)
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{
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return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
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}
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static bool find_hw_breakpoint(CPUState *cpu, target_ulong pc)
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{
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int i;
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for (i = 0; i < cur_hw_bps; i++) {
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HWBreakpoint *bp = get_hw_bp(i);
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if (bp->bvr == pc) {
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return true;
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}
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}
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return false;
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}
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static CPUWatchpoint *find_hw_watchpoint(CPUState *cpu, target_ulong addr)
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{
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int i;
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for (i = 0; i < cur_hw_wps; i++) {
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if (check_watchpoint_in_range(i, addr)) {
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return &get_hw_wp(i)->details;
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}
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}
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return NULL;
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}
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static bool kvm_arm_pmu_support_ctrl(CPUState *cs, struct kvm_device_attr *attr)
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{
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return kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr) == 0;
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}
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int kvm_arm_pmu_create(CPUState *cs, int irq)
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{
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int err;
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struct kvm_device_attr attr = {
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.group = KVM_ARM_VCPU_PMU_V3_CTRL,
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.addr = (intptr_t)&irq,
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.attr = KVM_ARM_VCPU_PMU_V3_IRQ,
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.flags = 0,
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};
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if (!kvm_arm_pmu_support_ctrl(cs, &attr)) {
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return 0;
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}
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err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, &attr);
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if (err < 0) {
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fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n",
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strerror(-err));
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abort();
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}
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attr.group = KVM_ARM_VCPU_PMU_V3_CTRL;
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attr.attr = KVM_ARM_VCPU_PMU_V3_INIT;
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attr.addr = 0;
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attr.flags = 0;
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err = kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, &attr);
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if (err < 0) {
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fprintf(stderr, "KVM_SET_DEVICE_ATTR failed: %s\n",
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strerror(-err));
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abort();
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}
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return 1;
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}
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static inline void set_feature(uint64_t *features, int feature)
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{
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*features |= 1ULL << feature;
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}
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bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
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{
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
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* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
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* For AArch64 we currently don't care about ID registers at
|
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* all; we just want to know the CPU type.
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*/
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int fdarray[3];
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uint64_t features = 0;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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* we know these will only support creating one kind of guest CPU,
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* which is its preferred CPU type. Fortunately these old kernels
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* support only a very limited number of CPUs.
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*/
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static const uint32_t cpus_to_try[] = {
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KVM_ARM_TARGET_AEM_V8,
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KVM_ARM_TARGET_FOUNDATION_V8,
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KVM_ARM_TARGET_CORTEX_A57,
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QEMU_KVM_ARM_TARGET_NONE
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};
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struct kvm_vcpu_init init;
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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return false;
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}
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ahcc->target = init.target;
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ahcc->dtb_compatible = "arm,arm-v8";
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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/* We can assume any KVM supporting CPU is at least a v8
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* with VFPv4+Neon; this in turn implies most of the other
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* feature bits.
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*/
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set_feature(&features, ARM_FEATURE_V8);
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set_feature(&features, ARM_FEATURE_VFP4);
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set_feature(&features, ARM_FEATURE_NEON);
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set_feature(&features, ARM_FEATURE_AARCH64);
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ahcc->features = features;
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return true;
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}
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#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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int ret;
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uint64_t mpidr;
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ARMCPU *cpu = ARM_CPU(cs);
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if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
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!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
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fprintf(stderr, "KVM is not supported for this guest CPU type\n");
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return -EINVAL;
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}
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|
|
/* Determine init features for this CPU */
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|
memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
|
|
if (cpu->start_powered_off) {
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
|
|
}
|
|
if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
|
|
cpu->psci_version = 2;
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
|
|
}
|
|
if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
|
|
}
|
|
if (kvm_irqchip_in_kernel() &&
|
|
kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
|
|
cpu->has_pmu = true;
|
|
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
|
|
}
|
|
|
|
/* Do KVM_ARM_VCPU_INIT ioctl */
|
|
ret = kvm_arm_vcpu_init(cs);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* When KVM is in use, PSCI is emulated in-kernel and not by qemu.
|
|
* Currently KVM has its own idea about MPIDR assignment, so we
|
|
* override our defaults with what we get from KVM.
|
|
*/
|
|
ret = kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
|
|
|
|
kvm_arm_init_debug(cs);
|
|
|
|
return kvm_arm_init_cpreg_list(cpu);
|
|
}
|
|
|
|
bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
|
|
{
|
|
/* Return true if the regidx is a register we should synchronize
|
|
* via the cpreg_tuples array (ie is not a core reg we sync by
|
|
* hand in kvm_arch_get/put_registers())
|
|
*/
|
|
switch (regidx & KVM_REG_ARM_COPROC_MASK) {
|
|
case KVM_REG_ARM_CORE:
|
|
return false;
|
|
default:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
typedef struct CPRegStateLevel {
|
|
uint64_t regidx;
|
|
int level;
|
|
} CPRegStateLevel;
|
|
|
|
/* All system registers not listed in the following table are assumed to be
|
|
* of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
|
|
* often, you must add it to this table with a state of either
|
|
* KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
|
|
*/
|
|
static const CPRegStateLevel non_runtime_cpregs[] = {
|
|
{ KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
|
|
};
|
|
|
|
int kvm_arm_cpreg_level(uint64_t regidx)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
|
|
const CPRegStateLevel *l = &non_runtime_cpregs[i];
|
|
if (l->regidx == regidx) {
|
|
return l->level;
|
|
}
|
|
}
|
|
|
|
return KVM_PUT_RUNTIME_STATE;
|
|
}
|
|
|
|
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
|
|
|
|
#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
|
|
|
|
#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
|
|
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
|
|
|
|
int kvm_arch_put_registers(CPUState *cs, int level)
|
|
{
|
|
struct kvm_one_reg reg;
|
|
uint32_t fpr;
|
|
uint64_t val;
|
|
int i;
|
|
int ret;
|
|
unsigned int el;
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
/* If we are in AArch32 mode then we need to copy the AArch32 regs to the
|
|
* AArch64 registers before pushing them out to 64-bit KVM.
|
|
*/
|
|
if (!is_a64(env)) {
|
|
aarch64_sync_32_to_64(env);
|
|
}
|
|
|
|
for (i = 0; i < 31; i++) {
|
|
reg.id = AARCH64_CORE_REG(regs.regs[i]);
|
|
reg.addr = (uintptr_t) &env->xregs[i];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
|
|
* QEMU side we keep the current SP in xregs[31] as well.
|
|
*/
|
|
aarch64_save_sp(env, 1);
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.sp);
|
|
reg.addr = (uintptr_t) &env->sp_el[0];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(sp_el1);
|
|
reg.addr = (uintptr_t) &env->sp_el[1];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
|
|
if (is_a64(env)) {
|
|
val = pstate_read(env);
|
|
} else {
|
|
val = cpsr_read(env);
|
|
}
|
|
reg.id = AARCH64_CORE_REG(regs.pstate);
|
|
reg.addr = (uintptr_t) &val;
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.pc);
|
|
reg.addr = (uintptr_t) &env->pc;
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(elr_el1);
|
|
reg.addr = (uintptr_t) &env->elr_el[1];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* Saved Program State Registers
|
|
*
|
|
* Before we restore from the banked_spsr[] array we need to
|
|
* ensure that any modifications to env->spsr are correctly
|
|
* reflected in the banks.
|
|
*/
|
|
el = arm_current_el(env);
|
|
if (el > 0 && !is_a64(env)) {
|
|
i = bank_number(env->uncached_cpsr & CPSR_M);
|
|
env->banked_spsr[i] = env->spsr;
|
|
}
|
|
|
|
/* KVM 0-4 map to QEMU banks 1-5 */
|
|
for (i = 0; i < KVM_NR_SPSR; i++) {
|
|
reg.id = AARCH64_CORE_REG(spsr[i]);
|
|
reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
/* Advanced SIMD and FP registers
|
|
* We map Qn = regs[2n+1]:regs[2n]
|
|
*/
|
|
for (i = 0; i < 32; i++) {
|
|
int rd = i << 1;
|
|
uint64_t fp_val[2];
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
|
fp_val[0] = env->vfp.regs[rd + 1];
|
|
fp_val[1] = env->vfp.regs[rd];
|
|
#else
|
|
fp_val[1] = env->vfp.regs[rd + 1];
|
|
fp_val[0] = env->vfp.regs[rd];
|
|
#endif
|
|
reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
|
|
reg.addr = (uintptr_t)(&fp_val);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
reg.addr = (uintptr_t)(&fpr);
|
|
fpr = vfp_get_fpsr(env);
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
fpr = vfp_get_fpcr(env);
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
if (!write_list_to_kvmstate(cpu, level)) {
|
|
return EINVAL;
|
|
}
|
|
|
|
kvm_arm_sync_mpstate_to_kvm(cpu);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int kvm_arch_get_registers(CPUState *cs)
|
|
{
|
|
struct kvm_one_reg reg;
|
|
uint64_t val;
|
|
uint32_t fpr;
|
|
unsigned int el;
|
|
int i;
|
|
int ret;
|
|
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
for (i = 0; i < 31; i++) {
|
|
reg.id = AARCH64_CORE_REG(regs.regs[i]);
|
|
reg.addr = (uintptr_t) &env->xregs[i];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.sp);
|
|
reg.addr = (uintptr_t) &env->sp_el[0];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(sp_el1);
|
|
reg.addr = (uintptr_t) &env->sp_el[1];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.pstate);
|
|
reg.addr = (uintptr_t) &val;
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
env->aarch64 = ((val & PSTATE_nRW) == 0);
|
|
if (is_a64(env)) {
|
|
pstate_write(env, val);
|
|
} else {
|
|
cpsr_write(env, val, 0xffffffff, CPSRWriteRaw);
|
|
}
|
|
|
|
/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
|
|
* QEMU side we keep the current SP in xregs[31] as well.
|
|
*/
|
|
aarch64_restore_sp(env, 1);
|
|
|
|
reg.id = AARCH64_CORE_REG(regs.pc);
|
|
reg.addr = (uintptr_t) &env->pc;
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* If we are in AArch32 mode then we need to sync the AArch32 regs with the
|
|
* incoming AArch64 regs received from 64-bit KVM.
|
|
* We must perform this after all of the registers have been acquired from
|
|
* the kernel.
|
|
*/
|
|
if (!is_a64(env)) {
|
|
aarch64_sync_64_to_32(env);
|
|
}
|
|
|
|
reg.id = AARCH64_CORE_REG(elr_el1);
|
|
reg.addr = (uintptr_t) &env->elr_el[1];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
|
|
/* Fetch the SPSR registers
|
|
*
|
|
* KVM SPSRs 0-4 map to QEMU banks 1-5
|
|
*/
|
|
for (i = 0; i < KVM_NR_SPSR; i++) {
|
|
reg.id = AARCH64_CORE_REG(spsr[i]);
|
|
reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
el = arm_current_el(env);
|
|
if (el > 0 && !is_a64(env)) {
|
|
i = bank_number(env->uncached_cpsr & CPSR_M);
|
|
env->spsr = env->banked_spsr[i];
|
|
}
|
|
|
|
/* Advanced SIMD and FP registers
|
|
* We map Qn = regs[2n+1]:regs[2n]
|
|
*/
|
|
for (i = 0; i < 32; i++) {
|
|
uint64_t fp_val[2];
|
|
reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
|
|
reg.addr = (uintptr_t)(&fp_val);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
} else {
|
|
int rd = i << 1;
|
|
#ifdef HOST_WORDS_BIGENDIAN
|
|
env->vfp.regs[rd + 1] = fp_val[0];
|
|
env->vfp.regs[rd] = fp_val[1];
|
|
#else
|
|
env->vfp.regs[rd + 1] = fp_val[1];
|
|
env->vfp.regs[rd] = fp_val[0];
|
|
#endif
|
|
}
|
|
}
|
|
|
|
reg.addr = (uintptr_t)(&fpr);
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
vfp_set_fpsr(env, fpr);
|
|
|
|
reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
|
|
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
vfp_set_fpcr(env, fpr);
|
|
|
|
if (!write_kvmstate_to_list(cpu)) {
|
|
return EINVAL;
|
|
}
|
|
/* Note that it's OK to have registers which aren't in CPUState,
|
|
* so we can ignore a failure return here.
|
|
*/
|
|
write_list_to_cpustate(cpu);
|
|
|
|
kvm_arm_sync_mpstate_to_qemu(cpu);
|
|
|
|
/* TODO: other registers */
|
|
return ret;
|
|
}
|
|
|
|
/* C6.6.29 BRK instruction */
|
|
static const uint32_t brk_insn = 0xd4200000;
|
|
|
|
int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
|
|
{
|
|
if (have_guest_debug) {
|
|
if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) ||
|
|
cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) {
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
} else {
|
|
error_report("guest debug not supported on this kernel");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
|
|
{
|
|
static uint32_t brk;
|
|
|
|
if (have_guest_debug) {
|
|
if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) ||
|
|
brk != brk_insn ||
|
|
cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1)) {
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
} else {
|
|
error_report("guest debug not supported on this kernel");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register
|
|
*
|
|
* To minimise translating between kernel and user-space the kernel
|
|
* ABI just provides user-space with the full exception syndrome
|
|
* register value to be decoded in QEMU.
|
|
*/
|
|
|
|
bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
|
|
{
|
|
int hsr_ec = debug_exit->hsr >> ARM_EL_EC_SHIFT;
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUClass *cc = CPU_GET_CLASS(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
/* Ensure PC is synchronised */
|
|
kvm_cpu_synchronize_state(cs);
|
|
|
|
switch (hsr_ec) {
|
|
case EC_SOFTWARESTEP:
|
|
if (cs->singlestep_enabled) {
|
|
return true;
|
|
} else {
|
|
/*
|
|
* The kernel should have suppressed the guest's ability to
|
|
* single step at this point so something has gone wrong.
|
|
*/
|
|
error_report("%s: guest single-step while debugging unsupported"
|
|
" (%"PRIx64", %"PRIx32")\n",
|
|
__func__, env->pc, debug_exit->hsr);
|
|
return false;
|
|
}
|
|
break;
|
|
case EC_AA64_BKPT:
|
|
if (kvm_find_sw_breakpoint(cs, env->pc)) {
|
|
return true;
|
|
}
|
|
break;
|
|
case EC_BREAKPOINT:
|
|
if (find_hw_breakpoint(cs, env->pc)) {
|
|
return true;
|
|
}
|
|
break;
|
|
case EC_WATCHPOINT:
|
|
{
|
|
CPUWatchpoint *wp = find_hw_watchpoint(cs, debug_exit->far);
|
|
if (wp) {
|
|
cs->watchpoint_hit = wp;
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")\n",
|
|
__func__, debug_exit->hsr, env->pc);
|
|
}
|
|
|
|
/* If we are not handling the debug exception it must belong to
|
|
* the guest. Let's re-use the existing TCG interrupt code to set
|
|
* everything up properly.
|
|
*/
|
|
cs->exception_index = EXCP_BKPT;
|
|
env->exception.syndrome = debug_exit->hsr;
|
|
env->exception.vaddress = debug_exit->far;
|
|
cc->do_interrupt(cs);
|
|
|
|
return false;
|
|
}
|