fa57e3274d
We don't actually do anything with most of the bits yet, but at least they have names and we have somewhere to store them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
192 lines
6 KiB
C
192 lines
6 KiB
C
/*
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* PA-RISC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HPPA_CPU_H
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#define HPPA_CPU_H
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#include "qemu-common.h"
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#include "cpu-qom.h"
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/* We only support hppa-linux-user at present, so 32-bit only. */
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#define TARGET_LONG_BITS 32
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define CPUArchState struct CPUHPPAState
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat.h"
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#define TARGET_PAGE_BITS 12
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#define ALIGNED_ONLY
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#define NB_MMU_MODES 1
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#define MMU_USER_IDX 0
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#define TARGET_INSN_START_EXTRA_WORDS 1
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#define EXCP_SYSCALL 1
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#define EXCP_SYSCALL_LWS 2
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#define EXCP_SIGSEGV 3
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#define EXCP_SIGILL 4
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#define EXCP_SIGFPE 5
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/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
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#define PSW_I 0x00000001
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#define PSW_D 0x00000002
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#define PSW_P 0x00000004
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#define PSW_Q 0x00000008
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#define PSW_R 0x00000010
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#define PSW_F 0x00000020
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#define PSW_G 0x00000040 /* PA1.x only */
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#define PSW_O 0x00000080 /* PA2.0 only */
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#define PSW_CB 0x0000ff00
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#define PSW_M 0x00010000
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#define PSW_V 0x00020000
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#define PSW_C 0x00040000
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#define PSW_B 0x00080000
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#define PSW_X 0x00100000
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#define PSW_N 0x00200000
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#define PSW_L 0x00400000
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#define PSW_H 0x00800000
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#define PSW_T 0x01000000
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#define PSW_S 0x02000000
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#define PSW_E 0x04000000
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#ifdef TARGET_HPPA64
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#define PSW_W 0x08000000 /* PA2.0 only */
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#else
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#define PSW_W 0
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#endif
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#define PSW_Z 0x40000000 /* PA1.x only */
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#define PSW_Y 0x80000000 /* PA1.x only */
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#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
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| PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
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/* ssm/rsm instructions number PSW_W and PSW_E differently */
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#define PSW_SM_I PSW_I /* Enable External Interrupts */
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#define PSW_SM_D PSW_D
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#define PSW_SM_P PSW_P
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#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
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#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
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#ifdef TARGET_HPPA64
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#define PSW_SM_E 0x100
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#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
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#else
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#define PSW_SM_E 0
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#define PSW_SM_W 0
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#endif
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typedef struct CPUHPPAState CPUHPPAState;
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struct CPUHPPAState {
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target_ulong gr[32];
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uint64_t fr[32];
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target_ulong sar;
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target_ulong cr26;
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target_ulong cr27;
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target_long psw; /* All psw bits except the following: */
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target_ulong psw_n; /* boolean */
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target_long psw_v; /* in most significant bit */
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/* Splitting the carry-borrow field into the MSB and "the rest", allows
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* for "the rest" to be deleted when it is unused, but the MSB is in use.
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* In addition, it's easier to compute carry-in for bit B+1 than it is to
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* compute carry-out for bit B (3 vs 4 insns for addition, assuming the
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* host has the appropriate add-with-carry insn to compute the msb).
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* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
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*/
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target_ulong psw_cb; /* in least significant bit of next nibble */
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target_ulong psw_cb_msb; /* boolean */
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target_ulong iaoq_f; /* front */
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target_ulong iaoq_b; /* back, aka next instruction */
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target_ulong ior; /* interrupt offset register */
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uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
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float_status fp_status;
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/* Those resources are used only in QEMU core */
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CPU_COMMON
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};
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/**
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* HPPACPU:
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* @env: #CPUHPPAState
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*
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* An HPPA CPU.
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*/
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struct HPPACPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUHPPAState env;
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};
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static inline HPPACPU *hppa_env_get_cpu(CPUHPPAState *env)
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{
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return container_of(env, HPPACPU, env);
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}
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#define ENV_GET_CPU(e) CPU(hppa_env_get_cpu(e))
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#define ENV_OFFSET offsetof(HPPACPU, env)
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#include "exec/cpu-all.h"
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static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
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{
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return 0;
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}
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void hppa_translate_init(void);
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#define cpu_init(cpu_model) cpu_generic_init(TYPE_HPPA_CPU, cpu_model)
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void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc,
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target_ulong *cs_base,
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uint32_t *pflags)
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{
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*pc = env->iaoq_f;
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*cs_base = env->iaoq_b;
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*pflags = env->psw_n;
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}
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target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
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void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
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void cpu_hppa_loaded_fr0(CPUHPPAState *env);
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#define cpu_signal_handler cpu_hppa_signal_handler
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int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc);
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int hppa_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
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int rw, int midx);
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hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
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int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void hppa_cpu_do_interrupt(CPUState *cpu);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function, int);
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#endif /* HPPA_CPU_H */
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