Max Filippov fa92bd4af7 target/xtensa: fix access to the INTERRUPT SR ... INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>		2019-01-24 10:44:26 -08:00
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bootparam.h	Clean up ill-advised or unusual header guards	2016-07-12 16:20:46 +02:00
Makefile.objs	hw/xtensa: extract xtensa_create_memory_regions	2018-01-11 09:31:26 -08:00
pic_cpu.c	target/xtensa: fix access to the INTERRUPT SR	2019-01-24 10:44:26 -08:00
sim.c	Change references to serial_hds[] to serial_hd()	2018-04-26 13:57:00 +01:00
xtensa_memory.c	hw/xtensa: extract xtensa_create_memory_regions	2018-01-11 09:31:26 -08:00
xtensa_memory.h	Clean up includes	2018-02-09 05:05:11 +01:00
xtfpga.c	hw/xtensa: xtfpga: use core frequency	2019-01-24 10:44:25 -08:00