Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
723 lines
23 KiB
C
723 lines
23 KiB
C
/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#define QEMU_GENERATE
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "tcg/tcg-op.h"
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#include "exec/cpu_ldst.h"
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#include "exec/log.h"
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#include "internal.h"
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#include "attribs.h"
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#include "insn.h"
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#include "decode.h"
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#include "translate.h"
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#include "printinsn.h"
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TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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TCGv hex_pred[NUM_PREGS];
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TCGv hex_next_PC;
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TCGv hex_this_PC;
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TCGv hex_slot_cancelled;
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TCGv hex_branch_taken;
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TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
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TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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TCGv hex_new_pred_value[NUM_PREGS];
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TCGv hex_pred_written;
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TCGv hex_store_addr[STORES_MAX];
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TCGv hex_store_width[STORES_MAX];
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TCGv hex_store_val32[STORES_MAX];
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TCGv_i64 hex_store_val64[STORES_MAX];
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TCGv hex_pkt_has_store_s1;
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TCGv hex_dczero_addr;
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TCGv hex_llsc_addr;
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TCGv hex_llsc_val;
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TCGv_i64 hex_llsc_val_i64;
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static const char * const hexagon_prednames[] = {
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"p0", "p1", "p2", "p3"
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};
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static void gen_exception_raw(int excp)
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{
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TCGv_i32 helper_tmp = tcg_const_i32(excp);
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gen_helper_raise_exception(cpu_env, helper_tmp);
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tcg_temp_free_i32(helper_tmp);
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}
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static void gen_exec_counters(DisasContext *ctx)
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{
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],
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hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets);
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tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT],
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hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);
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}
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static void gen_end_tb(DisasContext *ctx)
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{
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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if (ctx->base.singlestep_enabled) {
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gen_exception_raw(EXCP_DEBUG);
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} else {
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tcg_gen_exit_tb(NULL, 0);
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}
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_exception_end_tb(DisasContext *ctx, int excp)
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{
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gen_exec_counters(ctx);
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tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
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gen_exception_raw(excp);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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#define PACKET_BUFFER_LEN 1028
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static void print_pkt(Packet *pkt)
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{
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GString *buf = g_string_sized_new(PACKET_BUFFER_LEN);
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snprint_a_pkt_debug(buf, pkt);
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HEX_DEBUG_LOG("%s", buf->str);
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g_string_free(buf, true);
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}
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#define HEX_DEBUG_PRINT_PKT(pkt) \
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do { \
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if (HEX_DEBUG) { \
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print_pkt(pkt); \
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} \
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} while (0)
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static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
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uint32_t words[])
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{
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bool found_end = false;
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int nwords, max_words;
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memset(words, 0, PACKET_WORDS_MAX * sizeof(uint32_t));
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for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
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words[nwords] =
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translator_ldl(env, &ctx->base,
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ctx->base.pc_next + nwords * sizeof(uint32_t));
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found_end = is_packet_end(words[nwords]);
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}
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if (!found_end) {
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/* Read too many words without finding the end */
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return 0;
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}
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/* Check for page boundary crossing */
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max_words = -(ctx->base.pc_next | TARGET_PAGE_MASK) / sizeof(uint32_t);
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if (nwords > max_words) {
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/* We can only cross a page boundary at the beginning of a TB */
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g_assert(ctx->base.num_insns == 1);
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}
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HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next);
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HEX_DEBUG_LOG(" words = { ");
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for (int i = 0; i < nwords; i++) {
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HEX_DEBUG_LOG("0x%x, ", words[i]);
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}
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HEX_DEBUG_LOG("}\n");
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return nwords;
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}
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static bool check_for_attrib(Packet *pkt, int attrib)
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{
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for (int i = 0; i < pkt->num_insns; i++) {
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if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) {
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return true;
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}
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}
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return false;
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}
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static bool need_pc(Packet *pkt)
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{
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return check_for_attrib(pkt, A_IMPLICIT_READS_PC);
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}
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static bool need_slot_cancelled(Packet *pkt)
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{
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return check_for_attrib(pkt, A_CONDEXEC);
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}
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static bool need_pred_written(Packet *pkt)
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{
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return check_for_attrib(pkt, A_WRITES_PRED_REG);
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}
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static void gen_start_packet(DisasContext *ctx, Packet *pkt)
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{
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target_ulong next_PC = ctx->base.pc_next + pkt->encod_pkt_size_in_bytes;
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int i;
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/* Clear out the disassembly context */
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ctx->reg_log_idx = 0;
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bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);
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ctx->preg_log_idx = 0;
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bitmap_zero(ctx->pregs_written, NUM_PREGS);
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for (i = 0; i < STORES_MAX; i++) {
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ctx->store_width[i] = 0;
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}
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tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1);
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ctx->s1_store_processed = false;
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if (HEX_DEBUG) {
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/* Handy place to set a breakpoint before the packet executes */
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gen_helper_debug_start_packet(cpu_env);
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tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
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}
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/* Initialize the runtime state for packet semantics */
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if (need_pc(pkt)) {
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
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}
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if (need_slot_cancelled(pkt)) {
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tcg_gen_movi_tl(hex_slot_cancelled, 0);
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}
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if (pkt->pkt_has_cof) {
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tcg_gen_movi_tl(hex_branch_taken, 0);
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tcg_gen_movi_tl(hex_next_PC, next_PC);
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}
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if (need_pred_written(pkt)) {
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tcg_gen_movi_tl(hex_pred_written, 0);
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}
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}
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/*
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* The LOG_*_WRITE macros mark most of the writes in a packet
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* However, there are some implicit writes marked as attributes
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* of the applicable instructions.
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*/
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static void mark_implicit_reg_write(DisasContext *ctx, Insn *insn,
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int attrib, int rnum)
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{
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if (GET_ATTRIB(insn->opcode, attrib)) {
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bool is_predicated = GET_ATTRIB(insn->opcode, A_CONDEXEC);
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if (is_predicated && !is_preloaded(ctx, rnum)) {
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tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]);
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}
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ctx_log_reg_write(ctx, rnum);
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}
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}
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static void mark_implicit_pred_write(DisasContext *ctx, Insn *insn,
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int attrib, int pnum)
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{
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if (GET_ATTRIB(insn->opcode, attrib)) {
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ctx_log_pred_write(ctx, pnum);
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}
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}
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static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn)
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{
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LR, HEX_REG_LR);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC0, HEX_REG_LC0);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1);
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mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1);
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}
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static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn)
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{
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0);
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1);
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2);
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mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P3, 3);
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}
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static void gen_insn(CPUHexagonState *env, DisasContext *ctx,
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Insn *insn, Packet *pkt)
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{
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if (insn->generate) {
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mark_implicit_reg_writes(ctx, insn);
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insn->generate(env, ctx, insn, pkt);
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mark_implicit_pred_writes(ctx, insn);
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} else {
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gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE);
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}
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}
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/*
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* Helpers for generating the packet commit
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*/
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static void gen_reg_writes(DisasContext *ctx)
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{
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int i;
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for (i = 0; i < ctx->reg_log_idx; i++) {
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int reg_num = ctx->reg_log[i];
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tcg_gen_mov_tl(hex_gpr[reg_num], hex_new_value[reg_num]);
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}
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}
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static void gen_pred_writes(DisasContext *ctx, Packet *pkt)
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{
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int i;
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/* Early exit if the log is empty */
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if (!ctx->preg_log_idx) {
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return;
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}
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/*
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* Only endloop instructions will conditionally
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* write a predicate. If there are no endloop
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* instructions, we can use the non-conditional
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* write of the predicates.
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*/
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if (pkt->pkt_has_endloop) {
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TCGv zero = tcg_const_tl(0);
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TCGv pred_written = tcg_temp_new();
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for (i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pred_num);
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tcg_gen_movcond_tl(TCG_COND_NE, hex_pred[pred_num],
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pred_written, zero,
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hex_new_pred_value[pred_num],
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hex_pred[pred_num]);
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}
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tcg_temp_free(zero);
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tcg_temp_free(pred_written);
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} else {
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for (i = 0; i < ctx->preg_log_idx; i++) {
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int pred_num = ctx->preg_log[i];
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tcg_gen_mov_tl(hex_pred[pred_num], hex_new_pred_value[pred_num]);
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if (HEX_DEBUG) {
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/* Do this so HELPER(debug_commit_end) will know */
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tcg_gen_ori_tl(hex_pred_written, hex_pred_written,
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1 << pred_num);
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}
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}
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}
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}
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static void gen_check_store_width(DisasContext *ctx, int slot_num)
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{
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if (HEX_DEBUG) {
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TCGv slot = tcg_const_tl(slot_num);
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TCGv check = tcg_const_tl(ctx->store_width[slot_num]);
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gen_helper_debug_check_store_width(cpu_env, slot, check);
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tcg_temp_free(slot);
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tcg_temp_free(check);
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}
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}
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static bool slot_is_predicated(Packet *pkt, int slot_num)
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{
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for (int i = 0; i < pkt->num_insns; i++) {
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if (pkt->insn[i].slot == slot_num) {
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return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC);
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}
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}
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/* If we get to here, we didn't find an instruction in the requested slot */
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g_assert_not_reached();
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}
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void process_store(DisasContext *ctx, Packet *pkt, int slot_num)
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{
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bool is_predicated = slot_is_predicated(pkt, slot_num);
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TCGLabel *label_end = NULL;
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/*
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* We may have already processed this store
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* See CHECK_NOSHUF in macros.h
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*/
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if (slot_num == 1 && ctx->s1_store_processed) {
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return;
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}
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ctx->s1_store_processed = true;
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if (is_predicated) {
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TCGv cancelled = tcg_temp_new();
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label_end = gen_new_label();
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/* Don't do anything if the slot was cancelled */
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tcg_gen_extract_tl(cancelled, hex_slot_cancelled, slot_num, 1);
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tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
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tcg_temp_free(cancelled);
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}
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{
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TCGv address = tcg_temp_local_new();
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tcg_gen_mov_tl(address, hex_store_addr[slot_num]);
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/*
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* If we know the width from the DisasContext, we can
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* generate much cleaner code.
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* Unfortunately, not all instructions execute the fSTORE
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* macro during code generation. Anything that uses the
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* generic helper will have this problem. Instructions
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* that use fWRAP to generate proper TCG code will be OK.
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*/
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switch (ctx->store_width[slot_num]) {
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case 1:
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st8(hex_store_val32[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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break;
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case 2:
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st16(hex_store_val32[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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break;
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case 4:
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st32(hex_store_val32[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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break;
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case 8:
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gen_check_store_width(ctx, slot_num);
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tcg_gen_qemu_st64(hex_store_val64[slot_num],
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hex_store_addr[slot_num],
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ctx->mem_idx);
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break;
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default:
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{
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/*
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* If we get to here, we don't know the width at
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* TCG generation time, we'll use a helper to
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* avoid branching based on the width at runtime.
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*/
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TCGv slot = tcg_const_tl(slot_num);
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gen_helper_commit_store(cpu_env, slot);
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tcg_temp_free(slot);
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}
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}
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tcg_temp_free(address);
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}
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if (is_predicated) {
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gen_set_label(label_end);
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}
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}
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static void process_store_log(DisasContext *ctx, Packet *pkt)
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{
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/*
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* When a packet has two stores, the hardware processes
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* slot 1 and then slot 2. This will be important when
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* the memory accesses overlap.
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*/
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if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) {
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process_store(ctx, pkt, 1);
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}
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if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) {
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process_store(ctx, pkt, 0);
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}
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}
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/* Zero out a 32-bit cache line */
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static void process_dczeroa(DisasContext *ctx, Packet *pkt)
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{
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if (pkt->pkt_has_dczeroa) {
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/* Store 32 bytes of zero starting at (addr & ~0x1f) */
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TCGv addr = tcg_temp_new();
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TCGv_i64 zero = tcg_const_i64(0);
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tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st64(zero, addr, ctx->mem_idx);
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tcg_temp_free(addr);
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tcg_temp_free_i64(zero);
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}
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}
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static void update_exec_counters(DisasContext *ctx, Packet *pkt)
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{
|
|
int num_insns = pkt->num_insns;
|
|
int num_real_insns = 0;
|
|
|
|
for (int i = 0; i < num_insns; i++) {
|
|
if (!pkt->insn[i].is_endloop &&
|
|
!pkt->insn[i].part1 &&
|
|
!GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) {
|
|
num_real_insns++;
|
|
}
|
|
}
|
|
|
|
ctx->num_packets++;
|
|
ctx->num_insns += num_real_insns;
|
|
}
|
|
|
|
static void gen_commit_packet(DisasContext *ctx, Packet *pkt)
|
|
{
|
|
gen_reg_writes(ctx);
|
|
gen_pred_writes(ctx, pkt);
|
|
process_store_log(ctx, pkt);
|
|
process_dczeroa(ctx, pkt);
|
|
update_exec_counters(ctx, pkt);
|
|
if (HEX_DEBUG) {
|
|
TCGv has_st0 =
|
|
tcg_const_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa);
|
|
TCGv has_st1 =
|
|
tcg_const_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
|
|
|
|
/* Handy place to set a breakpoint at the end of execution */
|
|
gen_helper_debug_commit_end(cpu_env, has_st0, has_st1);
|
|
|
|
tcg_temp_free(has_st0);
|
|
tcg_temp_free(has_st1);
|
|
}
|
|
|
|
if (pkt->pkt_has_cof) {
|
|
gen_end_tb(ctx);
|
|
}
|
|
}
|
|
|
|
static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx)
|
|
{
|
|
uint32_t words[PACKET_WORDS_MAX];
|
|
int nwords;
|
|
Packet pkt;
|
|
int i;
|
|
|
|
nwords = read_packet_words(env, ctx, words);
|
|
if (!nwords) {
|
|
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
|
|
return;
|
|
}
|
|
|
|
if (decode_packet(nwords, words, &pkt, false) > 0) {
|
|
HEX_DEBUG_PRINT_PKT(&pkt);
|
|
gen_start_packet(ctx, &pkt);
|
|
for (i = 0; i < pkt.num_insns; i++) {
|
|
gen_insn(env, ctx, &pkt.insn[i], &pkt);
|
|
}
|
|
gen_commit_packet(ctx, &pkt);
|
|
ctx->base.pc_next += pkt.encod_pkt_size_in_bytes;
|
|
} else {
|
|
gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET);
|
|
}
|
|
}
|
|
|
|
static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,
|
|
CPUState *cs)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
ctx->mem_idx = MMU_USER_IDX;
|
|
ctx->num_packets = 0;
|
|
ctx->num_insns = 0;
|
|
}
|
|
|
|
static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)
|
|
{
|
|
}
|
|
|
|
static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
tcg_gen_insn_start(ctx->base.pc_next);
|
|
}
|
|
|
|
static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx)
|
|
{
|
|
target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
|
|
bool found_end = false;
|
|
int nwords;
|
|
|
|
for (nwords = 0; !found_end && nwords < PACKET_WORDS_MAX; nwords++) {
|
|
uint32_t word = cpu_ldl_code(env,
|
|
ctx->base.pc_next + nwords * sizeof(uint32_t));
|
|
found_end = is_packet_end(word);
|
|
}
|
|
uint32_t next_ptr = ctx->base.pc_next + nwords * sizeof(uint32_t);
|
|
return found_end && next_ptr - page_start >= TARGET_PAGE_SIZE;
|
|
}
|
|
|
|
static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
CPUHexagonState *env = cpu->env_ptr;
|
|
|
|
decode_and_translate_packet(env, ctx);
|
|
|
|
if (ctx->base.is_jmp == DISAS_NEXT) {
|
|
target_ulong page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
|
|
target_ulong bytes_max = PACKET_WORDS_MAX * sizeof(target_ulong);
|
|
|
|
if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE ||
|
|
(ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE - bytes_max &&
|
|
pkt_crosses_page(env, ctx))) {
|
|
ctx->base.is_jmp = DISAS_TOO_MANY;
|
|
}
|
|
|
|
/*
|
|
* The CPU log is used to compare against LLDB single stepping,
|
|
* so end the TLB after every packet.
|
|
*/
|
|
HexagonCPU *hex_cpu = env_archcpu(env);
|
|
if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
|
|
ctx->base.is_jmp = DISAS_TOO_MANY;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
DisasContext *ctx = container_of(dcbase, DisasContext, base);
|
|
|
|
switch (ctx->base.is_jmp) {
|
|
case DISAS_TOO_MANY:
|
|
gen_exec_counters(ctx);
|
|
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
|
|
if (ctx->base.singlestep_enabled) {
|
|
gen_exception_raw(EXCP_DEBUG);
|
|
} else {
|
|
tcg_gen_exit_tb(NULL, 0);
|
|
}
|
|
break;
|
|
case DISAS_NORETURN:
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static void hexagon_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
|
|
{
|
|
qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
|
|
log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
|
|
}
|
|
|
|
|
|
static const TranslatorOps hexagon_tr_ops = {
|
|
.init_disas_context = hexagon_tr_init_disas_context,
|
|
.tb_start = hexagon_tr_tb_start,
|
|
.insn_start = hexagon_tr_insn_start,
|
|
.translate_insn = hexagon_tr_translate_packet,
|
|
.tb_stop = hexagon_tr_tb_stop,
|
|
.disas_log = hexagon_tr_disas_log,
|
|
};
|
|
|
|
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
|
|
{
|
|
DisasContext ctx;
|
|
|
|
translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns);
|
|
}
|
|
|
|
#define NAME_LEN 64
|
|
static char new_value_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
|
|
static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN];
|
|
static char new_pred_value_names[NUM_PREGS][NAME_LEN];
|
|
static char store_addr_names[STORES_MAX][NAME_LEN];
|
|
static char store_width_names[STORES_MAX][NAME_LEN];
|
|
static char store_val32_names[STORES_MAX][NAME_LEN];
|
|
static char store_val64_names[STORES_MAX][NAME_LEN];
|
|
|
|
void hexagon_translate_init(void)
|
|
{
|
|
int i;
|
|
|
|
opcode_init();
|
|
|
|
if (HEX_DEBUG) {
|
|
if (!qemu_logfile) {
|
|
qemu_set_log(qemu_loglevel);
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
|
|
hex_gpr[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, gpr[i]),
|
|
hexagon_regnames[i]);
|
|
|
|
snprintf(new_value_names[i], NAME_LEN, "new_%s", hexagon_regnames[i]);
|
|
hex_new_value[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, new_value[i]),
|
|
new_value_names[i]);
|
|
|
|
if (HEX_DEBUG) {
|
|
snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
|
|
hexagon_regnames[i]);
|
|
hex_reg_written[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, reg_written[i]),
|
|
reg_written_names[i]);
|
|
}
|
|
}
|
|
for (i = 0; i < NUM_PREGS; i++) {
|
|
hex_pred[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, pred[i]),
|
|
hexagon_prednames[i]);
|
|
|
|
snprintf(new_pred_value_names[i], NAME_LEN, "new_pred_%s",
|
|
hexagon_prednames[i]);
|
|
hex_new_pred_value[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, new_pred_value[i]),
|
|
new_pred_value_names[i]);
|
|
}
|
|
hex_pred_written = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, pred_written), "pred_written");
|
|
hex_next_PC = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, next_PC), "next_PC");
|
|
hex_this_PC = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, this_PC), "this_PC");
|
|
hex_slot_cancelled = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
|
|
hex_branch_taken = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, branch_taken), "branch_taken");
|
|
hex_pkt_has_store_s1 = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, pkt_has_store_s1), "pkt_has_store_s1");
|
|
hex_dczero_addr = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, dczero_addr), "dczero_addr");
|
|
hex_llsc_addr = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
|
|
hex_llsc_val = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, llsc_val), "llsc_val");
|
|
hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
|
|
offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
|
|
for (i = 0; i < STORES_MAX; i++) {
|
|
snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
|
|
hex_store_addr[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, mem_log_stores[i].va),
|
|
store_addr_names[i]);
|
|
|
|
snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
|
|
hex_store_width[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, mem_log_stores[i].width),
|
|
store_width_names[i]);
|
|
|
|
snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i);
|
|
hex_store_val32[i] = tcg_global_mem_new(cpu_env,
|
|
offsetof(CPUHexagonState, mem_log_stores[i].data32),
|
|
store_val32_names[i]);
|
|
|
|
snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i);
|
|
hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env,
|
|
offsetof(CPUHexagonState, mem_log_stores[i].data64),
|
|
store_val64_names[i]);
|
|
}
|
|
}
|