Hardware support for VT-d device passthrough. Although current Linux can live with iommu=pt even without this, but this is faster than when using software passthrough. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Liu, Yi L <yi.l.liu@linux.intel.com> Reviewed-by: Jason Wang <jasowang@redhat.com>
446 lines
19 KiB
C
446 lines
19 KiB
C
/*
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* QEMU emulation of an Intel IOMMU (VT-d)
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* (DMA Remapping device)
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*
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* Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
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* Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Lots of defines copied from kernel/include/linux/intel-iommu.h:
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* Copyright (C) 2006-2008 Intel Corporation
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* Author: Ashok Raj <ashok.raj@intel.com>
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* Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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*
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*/
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#ifndef HW_I386_INTEL_IOMMU_INTERNAL_H
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#define HW_I386_INTEL_IOMMU_INTERNAL_H
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#include "hw/i386/intel_iommu.h"
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/*
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* Intel IOMMU register specification
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*/
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#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
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#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
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#define DMAR_CAP_REG_HI 0xc /* High 32-bit of DMAR_CAP_REG */
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#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
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#define DMAR_ECAP_REG_HI 0X14
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#define DMAR_GCMD_REG 0x18 /* Global command */
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#define DMAR_GSTS_REG 0x1c /* Global status */
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#define DMAR_RTADDR_REG 0x20 /* Root entry table */
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#define DMAR_RTADDR_REG_HI 0X24
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#define DMAR_CCMD_REG 0x28 /* Context command */
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#define DMAR_CCMD_REG_HI 0x2c
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#define DMAR_FSTS_REG 0x34 /* Fault status */
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#define DMAR_FECTL_REG 0x38 /* Fault control */
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#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data */
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#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr */
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#define DMAR_FEUADDR_REG 0x44 /* Upper address */
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#define DMAR_AFLOG_REG 0x58 /* Advanced fault control */
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#define DMAR_AFLOG_REG_HI 0X5c
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#define DMAR_PMEN_REG 0x64 /* Enable protected memory region */
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#define DMAR_PLMBASE_REG 0x68 /* PMRR low addr */
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#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
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#define DMAR_PHMBASE_REG 0x70 /* PMRR high base addr */
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#define DMAR_PHMBASE_REG_HI 0X74
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#define DMAR_PHMLIMIT_REG 0x78 /* PMRR high limit */
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#define DMAR_PHMLIMIT_REG_HI 0x7c
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#define DMAR_IQH_REG 0x80 /* Invalidation queue head */
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#define DMAR_IQH_REG_HI 0X84
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#define DMAR_IQT_REG 0x88 /* Invalidation queue tail */
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#define DMAR_IQT_REG_HI 0X8c
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#define DMAR_IQA_REG 0x90 /* Invalidation queue addr */
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#define DMAR_IQA_REG_HI 0x94
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#define DMAR_ICS_REG 0x9c /* Invalidation complete status */
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#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr */
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#define DMAR_IRTA_REG_HI 0xbc
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#define DMAR_IECTL_REG 0xa0 /* Invalidation event control */
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#define DMAR_IEDATA_REG 0xa4 /* Invalidation event data */
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#define DMAR_IEADDR_REG 0xa8 /* Invalidation event address */
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#define DMAR_IEUADDR_REG 0xac /* Invalidation event address */
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#define DMAR_PQH_REG 0xc0 /* Page request queue head */
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#define DMAR_PQH_REG_HI 0xc4
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#define DMAR_PQT_REG 0xc8 /* Page request queue tail*/
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#define DMAR_PQT_REG_HI 0xcc
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#define DMAR_PQA_REG 0xd0 /* Page request queue address */
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#define DMAR_PQA_REG_HI 0xd4
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#define DMAR_PRS_REG 0xdc /* Page request status */
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#define DMAR_PECTL_REG 0xe0 /* Page request event control */
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#define DMAR_PEDATA_REG 0xe4 /* Page request event data */
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#define DMAR_PEADDR_REG 0xe8 /* Page request event address */
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#define DMAR_PEUADDR_REG 0xec /* Page event upper address */
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#define DMAR_MTRRCAP_REG 0x100 /* MTRR capability */
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#define DMAR_MTRRCAP_REG_HI 0x104
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#define DMAR_MTRRDEF_REG 0x108 /* MTRR default type */
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#define DMAR_MTRRDEF_REG_HI 0x10c
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/* IOTLB registers */
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#define DMAR_IOTLB_REG_OFFSET 0xf0 /* Offset to the IOTLB registers */
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#define DMAR_IVA_REG DMAR_IOTLB_REG_OFFSET /* Invalidate address */
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#define DMAR_IVA_REG_HI (DMAR_IVA_REG + 4)
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/* IOTLB invalidate register */
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#define DMAR_IOTLB_REG (DMAR_IOTLB_REG_OFFSET + 0x8)
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#define DMAR_IOTLB_REG_HI (DMAR_IOTLB_REG + 4)
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/* FRCD */
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#define DMAR_FRCD_REG_OFFSET 0x220 /* Offset to the fault recording regs */
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/* NOTICE: If you change the DMAR_FRCD_REG_NR, please remember to change the
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* DMAR_REG_SIZE in include/hw/i386/intel_iommu.h.
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* #define DMAR_REG_SIZE (DMAR_FRCD_REG_OFFSET + 16 * DMAR_FRCD_REG_NR)
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*/
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#define DMAR_FRCD_REG_NR 1ULL /* Num of fault recording regs */
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#define DMAR_FRCD_REG_0_0 0x220 /* The 0th fault recording regs */
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#define DMAR_FRCD_REG_0_1 0x224
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#define DMAR_FRCD_REG_0_2 0x228
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#define DMAR_FRCD_REG_0_3 0x22c
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/* Interrupt Address Range */
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#define VTD_INTERRUPT_ADDR_FIRST 0xfee00000ULL
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#define VTD_INTERRUPT_ADDR_LAST 0xfeefffffULL
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#define VTD_INTERRUPT_ADDR_SIZE (VTD_INTERRUPT_ADDR_LAST - \
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VTD_INTERRUPT_ADDR_FIRST + 1)
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/* The shift of source_id in the key of IOTLB hash table */
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#define VTD_IOTLB_SID_SHIFT 36
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#define VTD_IOTLB_LVL_SHIFT 52
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#define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table */
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/* IOTLB_REG */
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#define VTD_TLB_GLOBAL_FLUSH (1ULL << 60) /* Global invalidation */
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#define VTD_TLB_DSI_FLUSH (2ULL << 60) /* Domain-selective */
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#define VTD_TLB_PSI_FLUSH (3ULL << 60) /* Page-selective */
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#define VTD_TLB_FLUSH_GRANU_MASK (3ULL << 60)
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#define VTD_TLB_GLOBAL_FLUSH_A (1ULL << 57)
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#define VTD_TLB_DSI_FLUSH_A (2ULL << 57)
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#define VTD_TLB_PSI_FLUSH_A (3ULL << 57)
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#define VTD_TLB_FLUSH_GRANU_MASK_A (3ULL << 57)
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#define VTD_TLB_IVT (1ULL << 63)
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#define VTD_TLB_DID(val) (((val) >> 32) & VTD_DOMAIN_ID_MASK)
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/* IVA_REG */
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#define VTD_IVA_ADDR(val) ((val) & ~0xfffULL & ((1ULL << VTD_MGAW) - 1))
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#define VTD_IVA_AM(val) ((val) & 0x3fULL)
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/* GCMD_REG */
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#define VTD_GCMD_TE (1UL << 31)
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#define VTD_GCMD_SRTP (1UL << 30)
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#define VTD_GCMD_SFL (1UL << 29)
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#define VTD_GCMD_EAFL (1UL << 28)
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#define VTD_GCMD_WBF (1UL << 27)
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#define VTD_GCMD_QIE (1UL << 26)
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#define VTD_GCMD_IRE (1UL << 25)
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#define VTD_GCMD_SIRTP (1UL << 24)
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#define VTD_GCMD_CFI (1UL << 23)
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/* GSTS_REG */
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#define VTD_GSTS_TES (1UL << 31)
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#define VTD_GSTS_RTPS (1UL << 30)
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#define VTD_GSTS_FLS (1UL << 29)
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#define VTD_GSTS_AFLS (1UL << 28)
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#define VTD_GSTS_WBFS (1UL << 27)
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#define VTD_GSTS_QIES (1UL << 26)
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#define VTD_GSTS_IRES (1UL << 25)
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#define VTD_GSTS_IRTPS (1UL << 24)
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#define VTD_GSTS_CFIS (1UL << 23)
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/* CCMD_REG */
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#define VTD_CCMD_ICC (1ULL << 63)
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#define VTD_CCMD_GLOBAL_INVL (1ULL << 61)
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#define VTD_CCMD_DOMAIN_INVL (2ULL << 61)
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#define VTD_CCMD_DEVICE_INVL (3ULL << 61)
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#define VTD_CCMD_CIRG_MASK (3ULL << 61)
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#define VTD_CCMD_GLOBAL_INVL_A (1ULL << 59)
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#define VTD_CCMD_DOMAIN_INVL_A (2ULL << 59)
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#define VTD_CCMD_DEVICE_INVL_A (3ULL << 59)
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#define VTD_CCMD_CAIG_MASK (3ULL << 59)
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#define VTD_CCMD_DID(val) ((val) & VTD_DOMAIN_ID_MASK)
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#define VTD_CCMD_SID(val) (((val) >> 16) & 0xffffULL)
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#define VTD_CCMD_FM(val) (((val) >> 32) & 3ULL)
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/* RTADDR_REG */
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#define VTD_RTADDR_RTT (1ULL << 11)
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#define VTD_RTADDR_ADDR_MASK (VTD_HAW_MASK ^ 0xfffULL)
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/* IRTA_REG */
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#define VTD_IRTA_ADDR_MASK (VTD_HAW_MASK ^ 0xfffULL)
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#define VTD_IRTA_EIME (1ULL << 11)
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#define VTD_IRTA_SIZE_MASK (0xfULL)
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/* ECAP_REG */
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/* (offset >> 4) << 8 */
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#define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4)
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#define VTD_ECAP_QI (1ULL << 1)
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#define VTD_ECAP_DT (1ULL << 2)
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/* Interrupt Remapping support */
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#define VTD_ECAP_IR (1ULL << 3)
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#define VTD_ECAP_EIM (1ULL << 4)
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#define VTD_ECAP_PT (1ULL << 6)
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#define VTD_ECAP_MHMV (15ULL << 20)
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/* CAP_REG */
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/* (offset >> 4) << 24 */
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#define VTD_CAP_FRO (DMAR_FRCD_REG_OFFSET << 20)
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#define VTD_CAP_NFR ((DMAR_FRCD_REG_NR - 1) << 40)
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#define VTD_DOMAIN_ID_SHIFT 16 /* 16-bit domain id for 64K domains */
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#define VTD_DOMAIN_ID_MASK ((1UL << VTD_DOMAIN_ID_SHIFT) - 1)
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#define VTD_CAP_ND (((VTD_DOMAIN_ID_SHIFT - 4) / 2) & 7ULL)
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#define VTD_MGAW 39 /* Maximum Guest Address Width */
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#define VTD_ADDRESS_SIZE (1ULL << VTD_MGAW)
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#define VTD_CAP_MGAW (((VTD_MGAW - 1) & 0x3fULL) << 16)
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#define VTD_MAMV 18ULL
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#define VTD_CAP_MAMV (VTD_MAMV << 48)
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#define VTD_CAP_PSI (1ULL << 39)
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#define VTD_CAP_SLLPS ((1ULL << 34) | (1ULL << 35))
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#define VTD_CAP_CM (1ULL << 7)
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/* Supported Adjusted Guest Address Widths */
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#define VTD_CAP_SAGAW_SHIFT 8
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#define VTD_CAP_SAGAW_MASK (0x1fULL << VTD_CAP_SAGAW_SHIFT)
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/* 39-bit AGAW, 3-level page-table */
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#define VTD_CAP_SAGAW_39bit (0x2ULL << VTD_CAP_SAGAW_SHIFT)
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/* 48-bit AGAW, 4-level page-table */
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#define VTD_CAP_SAGAW_48bit (0x4ULL << VTD_CAP_SAGAW_SHIFT)
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#define VTD_CAP_SAGAW VTD_CAP_SAGAW_39bit
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/* IQT_REG */
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#define VTD_IQT_QT(val) (((val) >> 4) & 0x7fffULL)
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/* IQA_REG */
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#define VTD_IQA_IQA_MASK (VTD_HAW_MASK ^ 0xfffULL)
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#define VTD_IQA_QS 0x7ULL
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/* IQH_REG */
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#define VTD_IQH_QH_SHIFT 4
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#define VTD_IQH_QH_MASK 0x7fff0ULL
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/* ICS_REG */
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#define VTD_ICS_IWC 1UL
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/* IECTL_REG */
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#define VTD_IECTL_IM (1UL << 31)
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#define VTD_IECTL_IP (1UL << 30)
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/* FSTS_REG */
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#define VTD_FSTS_FRI_MASK 0xff00UL
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#define VTD_FSTS_FRI(val) ((((uint32_t)(val)) << 8) & VTD_FSTS_FRI_MASK)
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#define VTD_FSTS_IQE (1UL << 4)
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#define VTD_FSTS_PPF (1UL << 1)
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#define VTD_FSTS_PFO 1UL
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/* FECTL_REG */
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#define VTD_FECTL_IM (1UL << 31)
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#define VTD_FECTL_IP (1UL << 30)
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/* Fault Recording Register */
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/* For the high 64-bit of 128-bit */
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#define VTD_FRCD_F (1ULL << 63)
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#define VTD_FRCD_T (1ULL << 62)
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#define VTD_FRCD_FR(val) (((val) & 0xffULL) << 32)
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#define VTD_FRCD_SID_MASK 0xffffULL
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#define VTD_FRCD_SID(val) ((val) & VTD_FRCD_SID_MASK)
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/* For the low 64-bit of 128-bit */
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#define VTD_FRCD_FI(val) ((val) & (((1ULL << VTD_MGAW) - 1) ^ 0xfffULL))
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/* DMA Remapping Fault Conditions */
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typedef enum VTDFaultReason {
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VTD_FR_RESERVED = 0, /* Reserved for Advanced Fault logging */
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VTD_FR_ROOT_ENTRY_P = 1, /* The Present(P) field of root-entry is 0 */
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VTD_FR_CONTEXT_ENTRY_P, /* The Present(P) field of context-entry is 0 */
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VTD_FR_CONTEXT_ENTRY_INV, /* Invalid programming of a context-entry */
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VTD_FR_ADDR_BEYOND_MGAW, /* Input-address above (2^x-1) */
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VTD_FR_WRITE, /* No write permission */
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VTD_FR_READ, /* No read permission */
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/* Fail to access a second-level paging entry (not SL_PML4E) */
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VTD_FR_PAGING_ENTRY_INV,
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VTD_FR_ROOT_TABLE_INV, /* Fail to access a root-entry */
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VTD_FR_CONTEXT_TABLE_INV, /* Fail to access a context-entry */
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/* Non-zero reserved field in a present root-entry */
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VTD_FR_ROOT_ENTRY_RSVD,
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/* Non-zero reserved field in a present context-entry */
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VTD_FR_CONTEXT_ENTRY_RSVD,
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/* Non-zero reserved field in a second-level paging entry with at lease one
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* Read(R) and Write(W) or Execute(E) field is Set.
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*/
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VTD_FR_PAGING_ENTRY_RSVD,
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/* Translation request or translated request explicitly blocked dut to the
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* programming of the Translation Type (T) field in the present
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* context-entry.
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*/
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VTD_FR_CONTEXT_ENTRY_TT,
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/* Interrupt remapping transition faults */
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VTD_FR_IR_REQ_RSVD = 0x20, /* One or more IR request reserved
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* fields set */
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VTD_FR_IR_INDEX_OVER = 0x21, /* Index value greater than max */
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VTD_FR_IR_ENTRY_P = 0x22, /* Present (P) not set in IRTE */
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VTD_FR_IR_ROOT_INVAL = 0x23, /* IR Root table invalid */
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VTD_FR_IR_IRTE_RSVD = 0x24, /* IRTE Rsvd field non-zero with
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* Present flag set */
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VTD_FR_IR_REQ_COMPAT = 0x25, /* Encountered compatible IR
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* request while disabled */
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VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
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/* This is not a normal fault reason. We use this to indicate some faults
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* that are not referenced by the VT-d specification.
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* Fault event with such reason should not be recorded.
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*/
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VTD_FR_RESERVED_ERR,
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VTD_FR_MAX, /* Guard */
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} VTDFaultReason;
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#define VTD_CONTEXT_CACHE_GEN_MAX 0xffffffffUL
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/* Interrupt Entry Cache Invalidation Descriptor: VT-d 6.5.2.7. */
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struct VTDInvDescIEC {
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uint32_t type:4; /* Should always be 0x4 */
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uint32_t granularity:1; /* If set, it's global IR invalidation */
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uint32_t resved_1:22;
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uint32_t index_mask:5; /* 2^N for continuous int invalidation */
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uint32_t index:16; /* Start index to invalidate */
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uint32_t reserved_2:16;
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};
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typedef struct VTDInvDescIEC VTDInvDescIEC;
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/* Queued Invalidation Descriptor */
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union VTDInvDesc {
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struct {
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uint64_t lo;
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uint64_t hi;
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};
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union {
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VTDInvDescIEC iec;
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};
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};
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typedef union VTDInvDesc VTDInvDesc;
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/* Masks for struct VTDInvDesc */
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#define VTD_INV_DESC_TYPE 0xf
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#define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */
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#define VTD_INV_DESC_IOTLB 0x2
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#define VTD_INV_DESC_DEVICE 0x3
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#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache
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Invalidate Descriptor */
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#define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */
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#define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */
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/* Masks for Invalidation Wait Descriptor*/
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#define VTD_INV_DESC_WAIT_SW (1ULL << 5)
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#define VTD_INV_DESC_WAIT_IF (1ULL << 4)
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#define VTD_INV_DESC_WAIT_FN (1ULL << 6)
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#define VTD_INV_DESC_WAIT_DATA_SHIFT 32
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#define VTD_INV_DESC_WAIT_RSVD_LO 0Xffffff80ULL
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#define VTD_INV_DESC_WAIT_RSVD_HI 3ULL
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/* Masks for Context-cache Invalidation Descriptor */
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#define VTD_INV_DESC_CC_G (3ULL << 4)
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#define VTD_INV_DESC_CC_GLOBAL (1ULL << 4)
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#define VTD_INV_DESC_CC_DOMAIN (2ULL << 4)
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#define VTD_INV_DESC_CC_DEVICE (3ULL << 4)
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#define VTD_INV_DESC_CC_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
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#define VTD_INV_DESC_CC_SID(val) (((val) >> 32) & 0xffffUL)
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#define VTD_INV_DESC_CC_FM(val) (((val) >> 48) & 3UL)
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#define VTD_INV_DESC_CC_RSVD 0xfffc00000000ffc0ULL
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/* Masks for IOTLB Invalidate Descriptor */
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#define VTD_INV_DESC_IOTLB_G (3ULL << 4)
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#define VTD_INV_DESC_IOTLB_GLOBAL (1ULL << 4)
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#define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4)
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#define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4)
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#define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_ID_MASK)
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#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL & \
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((1ULL << VTD_MGAW) - 1))
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#define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL)
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#define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL
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#define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL
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/* Mask for Device IOTLB Invalidate Descriptor */
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#define VTD_INV_DESC_DEVICE_IOTLB_ADDR(val) ((val) & 0xfffffffffffff000ULL)
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#define VTD_INV_DESC_DEVICE_IOTLB_SIZE(val) ((val) & 0x1)
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#define VTD_INV_DESC_DEVICE_IOTLB_SID(val) (((val) >> 32) & 0xFFFFULL)
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#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI 0xffeULL
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#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
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/* Information about page-selective IOTLB invalidate */
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struct VTDIOTLBPageInvInfo {
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uint16_t domain_id;
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uint64_t addr;
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uint8_t mask;
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};
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typedef struct VTDIOTLBPageInvInfo VTDIOTLBPageInvInfo;
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/* Pagesize of VTD paging structures, including root and context tables */
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#define VTD_PAGE_SHIFT 12
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#define VTD_PAGE_SIZE (1ULL << VTD_PAGE_SHIFT)
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#define VTD_PAGE_SHIFT_4K 12
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#define VTD_PAGE_MASK_4K (~((1ULL << VTD_PAGE_SHIFT_4K) - 1))
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#define VTD_PAGE_SHIFT_2M 21
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#define VTD_PAGE_MASK_2M (~((1ULL << VTD_PAGE_SHIFT_2M) - 1))
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#define VTD_PAGE_SHIFT_1G 30
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#define VTD_PAGE_MASK_1G (~((1ULL << VTD_PAGE_SHIFT_1G) - 1))
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struct VTDRootEntry {
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uint64_t val;
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uint64_t rsvd;
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};
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typedef struct VTDRootEntry VTDRootEntry;
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/* Masks for struct VTDRootEntry */
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#define VTD_ROOT_ENTRY_P 1ULL
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#define VTD_ROOT_ENTRY_CTP (~0xfffULL)
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#define VTD_ROOT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDRootEntry))
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#define VTD_ROOT_ENTRY_RSVD (0xffeULL | ~VTD_HAW_MASK)
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/* Masks for struct VTDContextEntry */
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/* lo */
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#define VTD_CONTEXT_ENTRY_P (1ULL << 0)
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#define VTD_CONTEXT_ENTRY_FPD (1ULL << 1) /* Fault Processing Disable */
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#define VTD_CONTEXT_ENTRY_TT (3ULL << 2) /* Translation Type */
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#define VTD_CONTEXT_TT_MULTI_LEVEL 0
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#define VTD_CONTEXT_TT_DEV_IOTLB (1ULL << 2)
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#define VTD_CONTEXT_TT_PASS_THROUGH (2ULL << 2)
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/* Second Level Page Translation Pointer*/
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#define VTD_CONTEXT_ENTRY_SLPTPTR (~0xfffULL)
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#define VTD_CONTEXT_ENTRY_RSVD_LO (0xff0ULL | ~VTD_HAW_MASK)
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/* hi */
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#define VTD_CONTEXT_ENTRY_AW 7ULL /* Adjusted guest-address-width */
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#define VTD_CONTEXT_ENTRY_DID(val) (((val) >> 8) & VTD_DOMAIN_ID_MASK)
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#define VTD_CONTEXT_ENTRY_RSVD_HI 0xffffffffff000080ULL
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#define VTD_CONTEXT_ENTRY_NR (VTD_PAGE_SIZE / sizeof(VTDContextEntry))
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/* Paging Structure common */
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#define VTD_SL_PT_PAGE_SIZE_MASK (1ULL << 7)
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/* Bits to decide the offset for each level */
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#define VTD_SL_LEVEL_BITS 9
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/* Second Level Paging Structure */
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#define VTD_SL_PML4_LEVEL 4
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#define VTD_SL_PDP_LEVEL 3
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#define VTD_SL_PD_LEVEL 2
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#define VTD_SL_PT_LEVEL 1
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#define VTD_SL_PT_ENTRY_NR 512
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/* Masks for Second Level Paging Entry */
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#define VTD_SL_RW_MASK 3ULL
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#define VTD_SL_R 1ULL
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#define VTD_SL_W (1ULL << 1)
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#define VTD_SL_PT_BASE_ADDR_MASK (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK)
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#define VTD_SL_IGN_COM 0xbff0000000000000ULL
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#endif
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