This is a mostly-mechanical conversion that creates a new flat union 'Netdev' QAPI type that covers all the branches of the former 'NetClientOptions' simple union, where the branches are now listed in a new 'NetClientDriver' enum rather than generated from the simple union. The existence of a flat union has no change to the command line syntax accepted for new code, and will make it possible for a future patch to switch the QMP command to parse a boxed union for no change to valid QMP; but it does have some ripple effect on the C code when dealing with the new types. While making the conversion, note that the 'NetLegacy' type remains unchanged: it applies only to legacy command line options, and will not be ported to QMP, so it should remain a wrapper around a simple union; to avoid confusion, the type named 'NetClientOptions' is now gone, and we introduce 'NetLegacyOptions' in its place. Then, in the C code, we convert from NetLegacy to Netdev as soon as possible, so that the bulk of the net stack only has to deal with one QAPI type, not two. Note that since the old legacy code always rejected 'hubport', we can just omit that branch from the new 'NetLegacyOptions' simple union. Based on an idea originally by Zoltán Kővágó <DirtY.iCE.hu@gmail.com>: Message-Id: <01a527fbf1a5de880091f98cf011616a78adeeee.1441627176.git.DirtY.iCE.hu@gmail.com> although the sed script in that patch no longer applies due to other changes in the tree since then, and I also did some manual cleanups (such as fixing whitespace to keep checkpatch happy). Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <1468468228-27827-13-git-send-email-eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> [Fixup from Eric squashed in] Signed-off-by: Markus Armbruster <armbru@redhat.com>
376 lines
11 KiB
C
376 lines
11 KiB
C
/*
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* QEMU AMD PC-Net II (Am79C970A) PCI emulation
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*
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* Copyright (c) 2004 Antony T Curtis
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* This software was written to be compatible with the specification:
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* AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
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* AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "net/net.h"
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#include "hw/loader.h"
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#include "qemu/timer.h"
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#include "sysemu/dma.h"
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#include "sysemu/sysemu.h"
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#include "trace.h"
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#include "pcnet.h"
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//#define PCNET_DEBUG
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//#define PCNET_DEBUG_IO
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//#define PCNET_DEBUG_BCR
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//#define PCNET_DEBUG_CSR
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//#define PCNET_DEBUG_RMD
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//#define PCNET_DEBUG_TMD
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//#define PCNET_DEBUG_MATCH
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#define TYPE_PCI_PCNET "pcnet"
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#define PCI_PCNET(obj) \
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OBJECT_CHECK(PCIPCNetState, (obj), TYPE_PCI_PCNET)
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typedef struct {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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PCNetState state;
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MemoryRegion io_bar;
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} PCIPCNetState;
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static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PCNetState *s = opaque;
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trace_pcnet_aprom_writeb(opaque, addr, val);
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if (BCR_APROMWE(s)) {
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s->prom[addr & 15] = val;
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}
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}
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static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
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{
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PCNetState *s = opaque;
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uint32_t val = s->prom[addr & 15];
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trace_pcnet_aprom_readb(opaque, addr, val);
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return val;
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}
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static uint64_t pcnet_ioport_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PCNetState *d = opaque;
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trace_pcnet_ioport_read(opaque, addr, size);
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if (addr < 0x10) {
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if (!BCR_DWIO(d) && size == 1) {
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return pcnet_aprom_readb(d, addr);
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} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
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return pcnet_aprom_readb(d, addr) |
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(pcnet_aprom_readb(d, addr + 1) << 8);
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} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
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return pcnet_aprom_readb(d, addr) |
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(pcnet_aprom_readb(d, addr + 1) << 8) |
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(pcnet_aprom_readb(d, addr + 2) << 16) |
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(pcnet_aprom_readb(d, addr + 3) << 24);
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}
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} else {
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if (size == 2) {
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return pcnet_ioport_readw(d, addr);
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} else if (size == 4) {
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return pcnet_ioport_readl(d, addr);
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}
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}
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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static void pcnet_ioport_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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PCNetState *d = opaque;
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trace_pcnet_ioport_write(opaque, addr, data, size);
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if (addr < 0x10) {
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if (!BCR_DWIO(d) && size == 1) {
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pcnet_aprom_writeb(d, addr, data);
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} else if (!BCR_DWIO(d) && (addr & 1) == 0 && size == 2) {
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pcnet_aprom_writeb(d, addr, data & 0xff);
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pcnet_aprom_writeb(d, addr + 1, data >> 8);
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} else if (BCR_DWIO(d) && (addr & 3) == 0 && size == 4) {
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pcnet_aprom_writeb(d, addr, data & 0xff);
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pcnet_aprom_writeb(d, addr + 1, (data >> 8) & 0xff);
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pcnet_aprom_writeb(d, addr + 2, (data >> 16) & 0xff);
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pcnet_aprom_writeb(d, addr + 3, data >> 24);
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}
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} else {
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if (size == 2) {
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pcnet_ioport_writew(d, addr, data);
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} else if (size == 4) {
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pcnet_ioport_writel(d, addr, data);
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}
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}
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}
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static const MemoryRegionOps pcnet_io_ops = {
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.read = pcnet_ioport_read,
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.write = pcnet_ioport_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
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{
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PCNetState *d = opaque;
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trace_pcnet_mmio_writeb(opaque, addr, val);
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if (!(addr & 0x10))
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pcnet_aprom_writeb(d, addr & 0x0f, val);
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}
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static uint32_t pcnet_mmio_readb(void *opaque, hwaddr addr)
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{
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PCNetState *d = opaque;
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uint32_t val = -1;
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if (!(addr & 0x10))
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val = pcnet_aprom_readb(d, addr & 0x0f);
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trace_pcnet_mmio_readb(opaque, addr, val);
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return val;
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}
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static void pcnet_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
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{
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PCNetState *d = opaque;
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trace_pcnet_mmio_writew(opaque, addr, val);
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if (addr & 0x10)
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pcnet_ioport_writew(d, addr & 0x0f, val);
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else {
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addr &= 0x0f;
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pcnet_aprom_writeb(d, addr, val & 0xff);
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pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
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}
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}
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static uint32_t pcnet_mmio_readw(void *opaque, hwaddr addr)
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{
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PCNetState *d = opaque;
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uint32_t val = -1;
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if (addr & 0x10)
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val = pcnet_ioport_readw(d, addr & 0x0f);
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else {
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addr &= 0x0f;
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val = pcnet_aprom_readb(d, addr+1);
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val <<= 8;
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val |= pcnet_aprom_readb(d, addr);
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}
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trace_pcnet_mmio_readw(opaque, addr, val);
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return val;
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}
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static void pcnet_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
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{
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PCNetState *d = opaque;
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trace_pcnet_mmio_writel(opaque, addr, val);
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if (addr & 0x10)
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pcnet_ioport_writel(d, addr & 0x0f, val);
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else {
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addr &= 0x0f;
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pcnet_aprom_writeb(d, addr, val & 0xff);
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pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
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pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
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pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
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}
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}
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static uint32_t pcnet_mmio_readl(void *opaque, hwaddr addr)
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{
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PCNetState *d = opaque;
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uint32_t val;
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if (addr & 0x10)
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val = pcnet_ioport_readl(d, addr & 0x0f);
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else {
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addr &= 0x0f;
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val = pcnet_aprom_readb(d, addr+3);
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val <<= 8;
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val |= pcnet_aprom_readb(d, addr+2);
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val <<= 8;
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val |= pcnet_aprom_readb(d, addr+1);
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val <<= 8;
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val |= pcnet_aprom_readb(d, addr);
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}
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trace_pcnet_mmio_readl(opaque, addr, val);
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return val;
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}
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static const VMStateDescription vmstate_pci_pcnet = {
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.name = "pcnet",
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.version_id = 3,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCIPCNetState),
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VMSTATE_STRUCT(state, PCIPCNetState, 0, vmstate_pcnet, PCNetState),
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VMSTATE_END_OF_LIST()
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}
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};
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/* PCI interface */
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static const MemoryRegionOps pcnet_mmio_ops = {
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.old_mmio = {
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.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
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.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
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uint8_t *buf, int len, int do_bswap)
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{
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pci_dma_write(dma_opaque, addr, buf, len);
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}
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static void pci_physical_memory_read(void *dma_opaque, hwaddr addr,
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uint8_t *buf, int len, int do_bswap)
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{
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pci_dma_read(dma_opaque, addr, buf, len);
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}
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static void pci_pcnet_uninit(PCIDevice *dev)
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{
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PCIPCNetState *d = PCI_PCNET(dev);
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qemu_free_irq(d->state.irq);
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timer_del(d->state.poll_timer);
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timer_free(d->state.poll_timer);
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qemu_del_nic(d->state.nic);
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}
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static NetClientInfo net_pci_pcnet_info = {
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.type = NET_CLIENT_DRIVER_NIC,
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.size = sizeof(NICState),
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.receive = pcnet_receive,
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.link_status_changed = pcnet_set_link_status,
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};
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static void pci_pcnet_realize(PCIDevice *pci_dev, Error **errp)
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{
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PCIPCNetState *d = PCI_PCNET(pci_dev);
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PCNetState *s = &d->state;
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uint8_t *pci_conf;
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#if 0
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printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
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sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
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#endif
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pci_conf = pci_dev->config;
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pci_set_word(pci_conf + PCI_STATUS,
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PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x0);
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pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0);
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pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
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pci_conf[PCI_MIN_GNT] = 0x06;
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pci_conf[PCI_MAX_LAT] = 0xff;
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/* Handler for memory-mapped I/O */
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memory_region_init_io(&d->state.mmio, OBJECT(d), &pcnet_mmio_ops, s,
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"pcnet-mmio", PCNET_PNPMMIO_SIZE);
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memory_region_init_io(&d->io_bar, OBJECT(d), &pcnet_io_ops, s, "pcnet-io",
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PCNET_IOPORT_SIZE);
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pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->io_bar);
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pci_register_bar(pci_dev, 1, 0, &s->mmio);
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s->irq = pci_allocate_irq(pci_dev);
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s->phys_mem_read = pci_physical_memory_read;
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s->phys_mem_write = pci_physical_memory_write;
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s->dma_opaque = pci_dev;
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pcnet_common_init(DEVICE(pci_dev), s, &net_pci_pcnet_info);
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}
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static void pci_reset(DeviceState *dev)
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{
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PCIPCNetState *d = PCI_PCNET(dev);
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pcnet_h_reset(&d->state);
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}
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static void pcnet_instance_init(Object *obj)
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{
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PCIPCNetState *d = PCI_PCNET(obj);
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PCNetState *s = &d->state;
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device_add_bootindex_property(obj, &s->conf.bootindex,
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"bootindex", "/ethernet-phy@0",
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DEVICE(obj), NULL);
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}
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static Property pcnet_properties[] = {
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DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pcnet_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = pci_pcnet_realize;
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k->exit = pci_pcnet_uninit;
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k->romfile = "efi-pcnet.rom",
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k->vendor_id = PCI_VENDOR_ID_AMD;
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k->device_id = PCI_DEVICE_ID_AMD_LANCE;
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k->revision = 0x10;
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k->class_id = PCI_CLASS_NETWORK_ETHERNET;
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dc->reset = pci_reset;
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dc->vmsd = &vmstate_pci_pcnet;
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dc->props = pcnet_properties;
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set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
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}
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static const TypeInfo pcnet_info = {
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.name = TYPE_PCI_PCNET,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIPCNetState),
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.class_init = pcnet_class_init,
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.instance_init = pcnet_instance_init,
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};
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static void pci_pcnet_register_types(void)
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{
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type_register_static(&pcnet_info);
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}
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type_init(pci_pcnet_register_types)
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