We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
185 lines
5.7 KiB
C
185 lines
5.7 KiB
C
/*
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* QEMU Xtensa CPU
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*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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cpu->env.pc = value;
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}
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static bool xtensa_cpu_has_work(CPUState *cs)
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{
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XtensaCPU *cpu = XTENSA_CPU(cs);
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return cpu->env.pending_irq_level;
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}
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/* CPUClass::reset() */
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static void xtensa_cpu_reset(CPUState *s)
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{
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XtensaCPU *cpu = XTENSA_CPU(s);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
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CPUXtensaState *env = &cpu->env;
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xcc->parent_reset(s);
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env->exception_taken = 0;
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env->pc = env->config->exception_vector[EXC_RESET];
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env->sregs[LITBASE] &= ~1;
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env->sregs[PS] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
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env->sregs[VECBASE] = env->config->vecbase;
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env->sregs[IBREAKENABLE] = 0;
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env->sregs[CACHEATTR] = 0x22222222;
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env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
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XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
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env->sregs[CONFIGID0] = env->config->configid[0];
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env->sregs[CONFIGID1] = env->config->configid[1];
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env->pending_irq_level = 0;
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reset_mmu(env);
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}
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static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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if (cpu_model == NULL) {
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return NULL;
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}
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typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
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object_class_is_abstract(oc)) {
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return NULL;
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}
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return oc;
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}
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static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
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qemu_init_vcpu(cs);
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xcc->parent_realize(dev, errp);
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}
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static void xtensa_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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XtensaCPU *cpu = XTENSA_CPU(obj);
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XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
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CPUXtensaState *env = &cpu->env;
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static bool tcg_inited;
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cs->env_ptr = env;
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env->config = xcc->config;
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if (tcg_enabled() && !tcg_inited) {
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tcg_inited = true;
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xtensa_translate_init();
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}
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}
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static const VMStateDescription vmstate_xtensa_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
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xcc->parent_realize = dc->realize;
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dc->realize = xtensa_cpu_realizefn;
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xcc->parent_reset = cc->reset;
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cc->reset = xtensa_cpu_reset;
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cc->class_by_name = xtensa_cpu_class_by_name;
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cc->has_work = xtensa_cpu_has_work;
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cc->do_interrupt = xtensa_cpu_do_interrupt;
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cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
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cc->dump_state = xtensa_cpu_dump_state;
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cc->set_pc = xtensa_cpu_set_pc;
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cc->gdb_read_register = xtensa_cpu_gdb_read_register;
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cc->gdb_write_register = xtensa_cpu_gdb_write_register;
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cc->gdb_stop_before_watchpoint = true;
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#ifndef CONFIG_USER_ONLY
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cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
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cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
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cc->do_unassigned_access = xtensa_cpu_do_unassigned_access;
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#endif
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cc->debug_excp_handler = xtensa_breakpoint_handler;
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dc->vmsd = &vmstate_xtensa_cpu;
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}
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static const TypeInfo xtensa_cpu_type_info = {
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.name = TYPE_XTENSA_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(XtensaCPU),
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.instance_init = xtensa_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(XtensaCPUClass),
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.class_init = xtensa_cpu_class_init,
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};
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static void xtensa_cpu_register_types(void)
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{
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type_register_static(&xtensa_cpu_type_info);
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}
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type_init(xtensa_cpu_register_types)
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