The following instructions are part of Zbc: - clmul - clmulh - clmulr Note that these instructions were already defined in the pre-0.93 and the 0.93 draft-B proposals, but had not been omitted in the earlier addition of draft-B to QEmu. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-10-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
568 lines
14 KiB
C++
568 lines
14 KiB
C++
/*
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* RISC-V translation routines for the Zb[acs] Standard Extension.
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*
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
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* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZBA(ctx) do { \
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if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_ZBC(ctx) do { \
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if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_ZBS(ctx) do { \
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if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
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return false; \
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} \
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} while (0)
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static void gen_clz(TCGv ret, TCGv arg1)
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{
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tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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static bool trans_clz(DisasContext *ctx, arg_clz *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_ZERO, gen_clz);
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}
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static void gen_ctz(TCGv ret, TCGv arg1)
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{
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tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
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}
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static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
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}
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static bool trans_andn(DisasContext *ctx, arg_andn *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
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}
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static bool trans_orn(DisasContext *ctx, arg_orn *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
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}
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static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
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}
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static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_deposit_tl(ret, arg1, arg2,
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TARGET_LONG_BITS / 2,
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TARGET_LONG_BITS / 2);
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}
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static bool trans_pack(DisasContext *ctx, arg_pack *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_pack);
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}
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static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
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tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
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tcg_temp_free(t);
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}
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static bool trans_packu(DisasContext *ctx, arg_packu *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packu);
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}
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static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_ext8u_tl(t, arg2);
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tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
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tcg_temp_free(t);
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}
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static bool trans_packh(DisasContext *ctx, arg_packh *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packh);
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}
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static bool trans_min(DisasContext *ctx, arg_min *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
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}
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static bool trans_max(DisasContext *ctx, arg_max *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
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}
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static bool trans_minu(DisasContext *ctx, arg_minu *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
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}
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static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
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}
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static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
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}
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static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
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}
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static void gen_sbop_mask(TCGv ret, TCGv shamt)
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{
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tcg_gen_movi_tl(ret, 1);
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tcg_gen_shl_tl(ret, ret, shamt);
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}
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static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
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{
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TCGv t = tcg_temp_new();
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gen_sbop_mask(t, shamt);
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tcg_gen_or_tl(ret, arg1, t);
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tcg_temp_free(t);
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}
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static bool trans_bset(DisasContext *ctx, arg_bset *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_bset);
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}
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static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
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}
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static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
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{
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TCGv t = tcg_temp_new();
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gen_sbop_mask(t, shamt);
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tcg_gen_andc_tl(ret, arg1, t);
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tcg_temp_free(t);
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}
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static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_bclr);
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}
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static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
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}
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static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
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{
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TCGv t = tcg_temp_new();
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gen_sbop_mask(t, shamt);
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tcg_gen_xor_tl(ret, arg1, t);
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tcg_temp_free(t);
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}
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static bool trans_binv(DisasContext *ctx, arg_binv *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_binv);
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}
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static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
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}
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static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
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{
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tcg_gen_shr_tl(ret, arg1, shamt);
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tcg_gen_andi_tl(ret, ret, 1);
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}
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static bool trans_bext(DisasContext *ctx, arg_bext *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift(ctx, a, EXT_NONE, gen_bext);
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}
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static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
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{
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REQUIRE_ZBS(ctx);
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
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}
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static bool trans_ror(DisasContext *ctx, arg_ror *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
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}
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static bool trans_rori(DisasContext *ctx, arg_rori *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
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}
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static bool trans_rol(DisasContext *ctx, arg_rol *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
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}
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static bool trans_grev(DisasContext *ctx, arg_grev *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
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}
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static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
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{
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if (shamt == TARGET_LONG_BITS - 8) {
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/* rev8, byte swaps */
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tcg_gen_bswap_tl(dest, src);
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} else {
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gen_helper_grev(dest, src, tcg_constant_tl(shamt));
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}
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}
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static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
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}
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static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
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}
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static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
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}
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#define GEN_SHADD(SHAMT) \
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static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
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{ \
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TCGv t = tcg_temp_new(); \
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\
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tcg_gen_shli_tl(t, arg1, SHAMT); \
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tcg_gen_add_tl(ret, t, arg2); \
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\
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tcg_temp_free(t); \
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}
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GEN_SHADD(1)
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GEN_SHADD(2)
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GEN_SHADD(3)
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#define GEN_TRANS_SHADD(SHAMT) \
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static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
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{ \
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REQUIRE_ZBA(ctx); \
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return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
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}
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GEN_TRANS_SHADD(1)
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GEN_TRANS_SHADD(2)
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GEN_TRANS_SHADD(3)
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static void gen_clzw(TCGv ret, TCGv arg1)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shli_tl(t, arg1, 32);
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tcg_gen_clzi_tl(ret, t, 32);
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tcg_temp_free(t);
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}
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static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_NONE, gen_clzw);
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}
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static void gen_ctzw(TCGv ret, TCGv arg1)
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{
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tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
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tcg_gen_ctzi_tl(ret, ret, 64);
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}
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static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
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}
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static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
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}
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static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_ext16s_tl(t, arg2);
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tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
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tcg_temp_free(t);
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}
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static bool trans_packw(DisasContext *ctx, arg_packw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packw);
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}
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static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shri_tl(t, arg1, 16);
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tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
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tcg_gen_ext32s_tl(ret, ret);
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tcg_temp_free(t);
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}
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static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packuw);
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}
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static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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/* truncate to 32-bits */
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tcg_gen_trunc_tl_i32(t1, arg1);
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tcg_gen_trunc_tl_i32(t2, arg2);
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tcg_gen_rotr_i32(t1, t1, t2);
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/* sign-extend 64-bits */
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tcg_gen_ext_i32_tl(ret, t1);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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}
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static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_NONE, gen_rorw);
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}
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static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
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}
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static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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/* truncate to 32-bits */
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tcg_gen_trunc_tl_i32(t1, arg1);
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tcg_gen_trunc_tl_i32(t2, arg2);
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tcg_gen_rotl_i32(t1, t1, t2);
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/* sign-extend 64-bits */
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tcg_gen_ext_i32_tl(ret, t1);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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}
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static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_NONE, gen_rolw);
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}
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static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
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}
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static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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ctx->w = true;
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return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_grev);
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}
|
|
|
|
static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
|
|
REQUIRE_EXT(ctx, RVB);
|
|
ctx->w = true;
|
|
return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
|
|
}
|
|
|
|
static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
|
|
REQUIRE_EXT(ctx, RVB);
|
|
ctx->w = true;
|
|
return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
|
|
}
|
|
|
|
#define GEN_SHADD_UW(SHAMT) \
|
|
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
|
|
{ \
|
|
TCGv t = tcg_temp_new(); \
|
|
\
|
|
tcg_gen_ext32u_tl(t, arg1); \
|
|
\
|
|
tcg_gen_shli_tl(t, t, SHAMT); \
|
|
tcg_gen_add_tl(ret, t, arg2); \
|
|
\
|
|
tcg_temp_free(t); \
|
|
}
|
|
|
|
GEN_SHADD_UW(1)
|
|
GEN_SHADD_UW(2)
|
|
GEN_SHADD_UW(3)
|
|
|
|
#define GEN_TRANS_SHADD_UW(SHAMT) \
|
|
static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
|
|
arg_sh##SHAMT##add_uw *a) \
|
|
{ \
|
|
REQUIRE_64BIT(ctx); \
|
|
REQUIRE_ZBA(ctx); \
|
|
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
|
|
}
|
|
|
|
GEN_TRANS_SHADD_UW(1)
|
|
GEN_TRANS_SHADD_UW(2)
|
|
GEN_TRANS_SHADD_UW(3)
|
|
|
|
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
|
|
{
|
|
TCGv t = tcg_temp_new();
|
|
tcg_gen_ext32u_tl(t, arg1);
|
|
tcg_gen_add_tl(ret, t, arg2);
|
|
tcg_temp_free(t);
|
|
}
|
|
|
|
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
|
|
REQUIRE_ZBA(ctx);
|
|
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
|
|
}
|
|
|
|
static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
|
|
{
|
|
tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
|
|
}
|
|
|
|
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
|
|
{
|
|
REQUIRE_64BIT(ctx);
|
|
REQUIRE_ZBA(ctx);
|
|
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
|
|
}
|
|
|
|
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
|
|
{
|
|
REQUIRE_ZBC(ctx);
|
|
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul);
|
|
}
|
|
|
|
static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
|
|
{
|
|
gen_helper_clmulr(dst, src1, src2);
|
|
tcg_gen_shri_tl(dst, dst, 1);
|
|
}
|
|
|
|
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
|
|
{
|
|
REQUIRE_ZBC(ctx);
|
|
return gen_arith(ctx, a, EXT_NONE, gen_clmulh);
|
|
}
|
|
|
|
static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
|
|
{
|
|
REQUIRE_ZBC(ctx);
|
|
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr);
|
|
}
|