Introduce csrr and csrw helpers, for read-only and write-only insns. Note that we do not properly implement this in riscv_csrrw, in that we cannot distinguish true read-only (rs1 == 0) from any other zero write_mask another source register -- this should still raise an exception for read-only registers. Only issue gen_io_start for CF_USE_ICOUNT. Use ctx->zero for csrrc. Use get_gpr and dest_gpr. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-19-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
576 lines
14 KiB
C++
576 lines
14 KiB
C++
/*
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* RISC-V translation routines for the RVXI Base Integer Instruction Set.
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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* Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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static bool trans_illegal(DisasContext *ctx, arg_empty *a)
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{
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gen_exception_illegal(ctx);
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return true;
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}
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static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
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{
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REQUIRE_64BIT(ctx);
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return trans_illegal(ctx, a);
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}
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static bool trans_lui(DisasContext *ctx, arg_lui *a)
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{
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if (a->rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
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}
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return true;
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}
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static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
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{
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if (a->rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
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}
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return true;
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}
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static bool trans_jal(DisasContext *ctx, arg_jal *a)
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{
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gen_jal(ctx, a->rd, a->imm);
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return true;
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}
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static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
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{
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TCGLabel *misaligned = NULL;
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tcg_gen_addi_tl(cpu_pc, get_gpr(ctx, a->rs1, EXT_NONE), a->imm);
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tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
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if (!has_ext(ctx, RVC)) {
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TCGv t0 = tcg_temp_new();
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misaligned = gen_new_label();
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tcg_gen_andi_tl(t0, cpu_pc, 0x2);
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tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
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tcg_temp_free(t0);
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}
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if (a->rd != 0) {
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tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
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}
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/* No chaining with JALR. */
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lookup_and_goto_ptr(ctx);
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if (misaligned) {
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gen_set_label(misaligned);
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gen_exception_inst_addr_mis(ctx);
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}
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
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{
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TCGLabel *l = gen_new_label();
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TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
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TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
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tcg_gen_brcond_tl(cond, src1, src2, l);
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gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
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gen_set_label(l); /* branch taken */
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if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) {
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/* misaligned */
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gen_exception_inst_addr_mis(ctx);
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} else {
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gen_goto_tb(ctx, 0, ctx->base.pc_next + a->imm);
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}
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_beq(DisasContext *ctx, arg_beq *a)
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{
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return gen_branch(ctx, a, TCG_COND_EQ);
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}
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static bool trans_bne(DisasContext *ctx, arg_bne *a)
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{
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return gen_branch(ctx, a, TCG_COND_NE);
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}
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static bool trans_blt(DisasContext *ctx, arg_blt *a)
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{
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return gen_branch(ctx, a, TCG_COND_LT);
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}
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static bool trans_bge(DisasContext *ctx, arg_bge *a)
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{
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return gen_branch(ctx, a, TCG_COND_GE);
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}
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static bool trans_bltu(DisasContext *ctx, arg_bltu *a)
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{
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return gen_branch(ctx, a, TCG_COND_LTU);
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}
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static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
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{
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return gen_branch(ctx, a, TCG_COND_GEU);
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}
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static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
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{
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TCGv dest = dest_gpr(ctx, a->rd);
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TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
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if (a->imm) {
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TCGv temp = temp_new(ctx);
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
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gen_set_gpr(ctx, a->rd, dest);
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return true;
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}
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static bool trans_lb(DisasContext *ctx, arg_lb *a)
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{
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return gen_load(ctx, a, MO_SB);
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}
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static bool trans_lh(DisasContext *ctx, arg_lh *a)
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{
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return gen_load(ctx, a, MO_TESW);
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}
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static bool trans_lw(DisasContext *ctx, arg_lw *a)
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{
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return gen_load(ctx, a, MO_TESL);
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}
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static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
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{
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return gen_load(ctx, a, MO_UB);
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}
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static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
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{
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return gen_load(ctx, a, MO_TEUW);
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}
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static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
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{
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TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
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TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
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if (a->imm) {
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TCGv temp = temp_new(ctx);
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
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return true;
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}
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static bool trans_sb(DisasContext *ctx, arg_sb *a)
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{
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return gen_store(ctx, a, MO_SB);
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}
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static bool trans_sh(DisasContext *ctx, arg_sh *a)
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{
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return gen_store(ctx, a, MO_TESW);
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}
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static bool trans_sw(DisasContext *ctx, arg_sw *a)
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{
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return gen_store(ctx, a, MO_TESL);
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}
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static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_load(ctx, a, MO_TEUL);
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}
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static bool trans_ld(DisasContext *ctx, arg_ld *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_load(ctx, a, MO_TEQ);
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}
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static bool trans_sd(DisasContext *ctx, arg_sd *a)
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{
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REQUIRE_64BIT(ctx);
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return gen_store(ctx, a, MO_TEQ);
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}
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static bool trans_addi(DisasContext *ctx, arg_addi *a)
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{
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return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
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}
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static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
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{
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tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
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}
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static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
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{
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tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
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}
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static bool trans_slti(DisasContext *ctx, arg_slti *a)
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{
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return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
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}
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static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
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{
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return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
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}
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static bool trans_xori(DisasContext *ctx, arg_xori *a)
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{
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return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
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}
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static bool trans_ori(DisasContext *ctx, arg_ori *a)
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{
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return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
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}
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static bool trans_andi(DisasContext *ctx, arg_andi *a)
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{
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return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
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}
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static bool trans_slli(DisasContext *ctx, arg_slli *a)
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{
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return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
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}
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static bool trans_srli(DisasContext *ctx, arg_srli *a)
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{
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return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
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}
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static bool trans_srai(DisasContext *ctx, arg_srai *a)
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{
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return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
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}
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static bool trans_add(DisasContext *ctx, arg_add *a)
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{
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
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}
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static bool trans_sub(DisasContext *ctx, arg_sub *a)
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{
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
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}
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static bool trans_sll(DisasContext *ctx, arg_sll *a)
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{
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return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
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}
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static bool trans_slt(DisasContext *ctx, arg_slt *a)
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{
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return gen_arith(ctx, a, EXT_SIGN, gen_slt);
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}
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static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
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{
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return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
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}
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static bool trans_xor(DisasContext *ctx, arg_xor *a)
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{
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
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}
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static bool trans_srl(DisasContext *ctx, arg_srl *a)
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{
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return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
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}
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static bool trans_sra(DisasContext *ctx, arg_sra *a)
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{
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return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
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}
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static bool trans_or(DisasContext *ctx, arg_or *a)
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{
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
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}
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static bool trans_and(DisasContext *ctx, arg_and *a)
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{
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
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}
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static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
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}
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static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
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}
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static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
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{
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tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
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}
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static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
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}
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static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
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{
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tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
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}
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static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
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}
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static bool trans_addw(DisasContext *ctx, arg_addw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
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}
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static bool trans_subw(DisasContext *ctx, arg_subw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
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}
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static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
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}
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static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
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}
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static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
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{
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REQUIRE_64BIT(ctx);
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ctx->w = true;
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return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
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}
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static bool trans_fence(DisasContext *ctx, arg_fence *a)
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{
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/* FENCE is a full memory barrier. */
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
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return true;
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}
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static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
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{
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if (!ctx->ext_ifencei) {
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return false;
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}
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/*
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* FENCE_I is a no-op in QEMU,
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* however we need to end the translation block
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*/
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
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exit_tb(ctx);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool do_csr_post(DisasContext *ctx)
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{
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/* We may have changed important cpu state -- exit to main loop. */
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tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
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exit_tb(ctx);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool do_csrr(DisasContext *ctx, int rd, int rc)
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{
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TCGv dest = dest_gpr(ctx, rd);
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TCGv_i32 csr = tcg_constant_i32(rc);
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if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_csrr(dest, cpu_env, csr);
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gen_set_gpr(ctx, rd, dest);
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return do_csr_post(ctx);
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}
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static bool do_csrw(DisasContext *ctx, int rc, TCGv src)
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{
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TCGv_i32 csr = tcg_constant_i32(rc);
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if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_csrw(cpu_env, csr, src);
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return do_csr_post(ctx);
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}
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static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
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{
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TCGv dest = dest_gpr(ctx, rd);
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TCGv_i32 csr = tcg_constant_i32(rc);
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if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_csrrw(dest, cpu_env, csr, src, mask);
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gen_set_gpr(ctx, rd, dest);
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return do_csr_post(ctx);
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}
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static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
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{
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TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
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/*
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* If rd == 0, the insn shall not read the csr, nor cause any of the
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* side effects that might occur on a csr read.
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*/
|
|
if (a->rd == 0) {
|
|
return do_csrw(ctx, a->csr, src);
|
|
}
|
|
|
|
TCGv mask = tcg_constant_tl(-1);
|
|
return do_csrrw(ctx, a->rd, a->csr, src, mask);
|
|
}
|
|
|
|
static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
|
|
{
|
|
/*
|
|
* If rs1 == 0, the insn shall not write to the csr at all, nor
|
|
* cause any of the side effects that might occur on a csr write.
|
|
* Note that if rs1 specifies a register other than x0, holding
|
|
* a zero value, the instruction will still attempt to write the
|
|
* unmodified value back to the csr and will cause side effects.
|
|
*/
|
|
if (a->rs1 == 0) {
|
|
return do_csrr(ctx, a->rd, a->csr);
|
|
}
|
|
|
|
TCGv ones = tcg_constant_tl(-1);
|
|
TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
|
|
return do_csrrw(ctx, a->rd, a->csr, ones, mask);
|
|
}
|
|
|
|
static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
|
|
{
|
|
/*
|
|
* If rs1 == 0, the insn shall not write to the csr at all, nor
|
|
* cause any of the side effects that might occur on a csr write.
|
|
* Note that if rs1 specifies a register other than x0, holding
|
|
* a zero value, the instruction will still attempt to write the
|
|
* unmodified value back to the csr and will cause side effects.
|
|
*/
|
|
if (a->rs1 == 0) {
|
|
return do_csrr(ctx, a->rd, a->csr);
|
|
}
|
|
|
|
TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
|
|
return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
|
|
}
|
|
|
|
static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
|
|
{
|
|
TCGv src = tcg_constant_tl(a->rs1);
|
|
|
|
/*
|
|
* If rd == 0, the insn shall not read the csr, nor cause any of the
|
|
* side effects that might occur on a csr read.
|
|
*/
|
|
if (a->rd == 0) {
|
|
return do_csrw(ctx, a->csr, src);
|
|
}
|
|
|
|
TCGv mask = tcg_constant_tl(-1);
|
|
return do_csrrw(ctx, a->rd, a->csr, src, mask);
|
|
}
|
|
|
|
static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
|
|
{
|
|
/*
|
|
* If rs1 == 0, the insn shall not write to the csr at all, nor
|
|
* cause any of the side effects that might occur on a csr write.
|
|
* Note that if rs1 specifies a register other than x0, holding
|
|
* a zero value, the instruction will still attempt to write the
|
|
* unmodified value back to the csr and will cause side effects.
|
|
*/
|
|
if (a->rs1 == 0) {
|
|
return do_csrr(ctx, a->rd, a->csr);
|
|
}
|
|
|
|
TCGv ones = tcg_constant_tl(-1);
|
|
TCGv mask = tcg_constant_tl(a->rs1);
|
|
return do_csrrw(ctx, a->rd, a->csr, ones, mask);
|
|
}
|
|
|
|
static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
|
|
{
|
|
/*
|
|
* If rs1 == 0, the insn shall not write to the csr at all, nor
|
|
* cause any of the side effects that might occur on a csr write.
|
|
* Note that if rs1 specifies a register other than x0, holding
|
|
* a zero value, the instruction will still attempt to write the
|
|
* unmodified value back to the csr and will cause side effects.
|
|
*/
|
|
if (a->rs1 == 0) {
|
|
return do_csrr(ctx, a->rd, a->csr);
|
|
}
|
|
|
|
TCGv mask = tcg_constant_tl(a->rs1);
|
|
return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
|
|
}
|