Alistair Francis fda5b000fa riscv/sifive_u: Add a serial property to the sifive_u SoC ... At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to the sifive_u SoC to specify the board serial number. When not given, the default serial number 1 is used. Suggested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>		2020-04-29 13:16:36 -07:00
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boot.c	hw/core/loader: Let load_elf() populate a field with CPU-specific flags	2020-01-29 19:28:52 +01:00
Kconfig	riscv: virt: Use Goldfish RTC device	2020-02-10 12:01:38 -08:00
Makefile.objs	riscv: sifive: Implement a model for SiFive FU540 OTP	2019-09-17 08:42:49 -07:00
riscv_hart.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_clint.c	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00
sifive_e.c	hw/riscv: Let devices own the MemoryRegion they create	2020-03-17 15:18:49 +01:00
sifive_e_prci.c	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_gpio.c	Include migration/vmstate.h less	2019-08-16 13:31:52 +02:00
sifive_plic.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_test.c	riscv: hw: Remove the unnecessary include of target/riscv/cpu.h	2019-09-17 08:42:45 -07:00
sifive_u.c	riscv/sifive_u: Add a serial property to the sifive_u SoC	2020-04-29 13:16:36 -07:00
sifive_u_otp.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_u_prci.c	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	RISC-V Patches for the 5.0 Soft Freeze, Part 3	2020-03-03 11:06:39 +00:00
trace-events	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
virt.c	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00