Hou Weiying fdd33b86b2 riscv: Fix bug in setting pmpcfg CSR for RISCV64 ... First, sizeof(target_ulong) equals to 4 on riscv32, so this change does not change the function on riscv32. Second, sizeof(target_ulong) equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal pmp_index (we will explain later), which should be 'reg_index * 4 + i'. If the parameter reg_index equals to 2 (means that we will change the value of pmpcfg2, or the second pmpcfg on riscv64), then pmpcfg_csr_write(env, 2, val) will map write tasks to pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed by value 16 or 23 on riscv64, so we consider it as a bug. We are looking for constant (e.g., define a new constant named RISCV_WORD_SIZE) in QEMU to help others understand code better, but none was found. A possible good explanation of this literal is it is the minimum word length on riscv is 4 bytes (32 bit). Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com> Signed-off-by: Hou Weiying <weiying_hou@outlook.com> Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <SG2PR02MB263420036254AC8841F66CE393460@SG2PR02MB2634.apcprd02.prod.outlook.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-08-21 22:37:55 -07:00
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insn_trans	target/riscv: check before allocating TCG temps	2020-08-21 22:37:55 -07:00
cpu-param.h	tcg: Split out target/arch/cpu-param.h	2019-06-10 07:03:34 -07:00
cpu.c	target/riscv: configure and turn on vector extension from command line	2020-07-02 09:19:34 -07:00
cpu.h	target/riscv: fix vill bit index in vtype register	2020-07-13 17:25:37 -07:00
cpu_bits.h	target/riscv: support vector extension csr	2020-07-02 09:19:32 -07:00
cpu_helper.c	target/riscv: Report errors validating 2nd-stage PTEs	2020-06-19 08:24:07 -07:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	target/riscv: Fix the range of pmpcfg of CSR funcion table	2020-07-22 09:41:36 -07:00
fpu_helper.c	target/riscv: Check nanboxed inputs to fp helpers	2020-08-21 22:37:55 -07:00
gdbstub.c	gdbstub: extend GByteArray to read register helpers	2020-03-17 17:38:38 +00:00
helper.h	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn16.decode	target/riscv: Add checks for several RVC reserved operands	2019-05-24 12:09:25 -07:00
insn32-64.decode	target/riscv: add vector amo operations	2020-07-02 09:19:33 -07:00
insn32.decode	target/riscv: vector compress instruction	2020-07-02 09:19:34 -07:00
instmap.h	target/riscv: progressively load the instruction during decode	2020-02-25 20:20:23 +00:00
internals.h	target/riscv: Check nanboxed inputs to fp helpers	2020-08-21 22:37:55 -07:00
meson.build	meson: target	2020-08-21 06:30:35 -04:00
monitor.c	target/riscv: Drop support for ISA spec version 1.09.1	2020-06-03 09:11:51 -07:00
op_helper.c	target/riscv: Implement checks for hfence	2020-06-19 08:24:07 -07:00
pmp.c	riscv: Fix bug in setting pmpcfg CSR for RISCV64	2020-08-21 22:37:55 -07:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-06-23 23:44:41 -07:00
trace-events	target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events	2019-09-17 08:42:42 -07:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Check nanboxed inputs in trans_rvf.inc.c	2020-08-21 22:37:55 -07:00
vector_helper.c	target/riscv/vector_helper: Fix build on 32-bit big endian hosts	2020-08-05 10:43:45 +02:00