Several block device properties related to blocksize configuration must be in certain relationship WRT each other: physical block must be no smaller than logical block; min_io_size, opt_io_size, and discard_granularity must be a multiple of a logical block. To ensure these requirements are met, add corresponding consistency checks to blkconf_blocksizes, adjusting its signature to communicate possible error to the caller. Also remove the now redundant consistency checks from the specific devices. Signed-off-by: Roman Kagan <rvkagan@yandex-team.ru> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Message-Id: <20200528225516.1676602-3-rvkagan@yandex-team.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
493 lines
13 KiB
C
493 lines
13 KiB
C
/*
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* QEMU Macintosh floppy disk controller emulator (SWIM)
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*
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* Copyright (c) 2014-2018 Laurent Vivier <laurent@vivier.eu>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Only the basic support: it allows to switch from IWM (Integrated WOZ
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* Machine) mode to the SWIM mode and makes the linux driver happy.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "qapi/error.h"
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#include "sysemu/block-backend.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/block/block.h"
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#include "hw/block/swim.h"
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#include "hw/qdev-properties.h"
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/* IWM registers */
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#define IWM_PH0L 0
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#define IWM_PH0H 1
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#define IWM_PH1L 2
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#define IWM_PH1H 3
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#define IWM_PH2L 4
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#define IWM_PH2H 5
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#define IWM_PH3L 6
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#define IWM_PH3H 7
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#define IWM_MTROFF 8
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#define IWM_MTRON 9
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#define IWM_INTDRIVE 10
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#define IWM_EXTDRIVE 11
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#define IWM_Q6L 12
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#define IWM_Q6H 13
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#define IWM_Q7L 14
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#define IWM_Q7H 15
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/* SWIM registers */
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#define SWIM_WRITE_DATA 0
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#define SWIM_WRITE_MARK 1
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#define SWIM_WRITE_CRC 2
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#define SWIM_WRITE_PARAMETER 3
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#define SWIM_WRITE_PHASE 4
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#define SWIM_WRITE_SETUP 5
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#define SWIM_WRITE_MODE0 6
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#define SWIM_WRITE_MODE1 7
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#define SWIM_READ_DATA 8
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#define SWIM_READ_MARK 9
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#define SWIM_READ_ERROR 10
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#define SWIM_READ_PARAMETER 11
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#define SWIM_READ_PHASE 12
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#define SWIM_READ_SETUP 13
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#define SWIM_READ_STATUS 14
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#define SWIM_READ_HANDSHAKE 15
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#define REG_SHIFT 9
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#define SWIM_MODE_IWM 0
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#define SWIM_MODE_SWIM 1
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/* bits in phase register */
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#define SWIM_SEEK_NEGATIVE 0x074
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#define SWIM_STEP 0x071
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#define SWIM_MOTOR_ON 0x072
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#define SWIM_MOTOR_OFF 0x076
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#define SWIM_INDEX 0x073
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#define SWIM_EJECT 0x077
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#define SWIM_SETMFM 0x171
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#define SWIM_SETGCR 0x175
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#define SWIM_RELAX 0x033
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#define SWIM_LSTRB 0x008
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#define SWIM_CA_MASK 0x077
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/* Select values for swim_select and swim_readbit */
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#define SWIM_READ_DATA_0 0x074
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#define SWIM_TWOMEG_DRIVE 0x075
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#define SWIM_SINGLE_SIDED 0x076
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#define SWIM_DRIVE_PRESENT 0x077
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#define SWIM_DISK_IN 0x170
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#define SWIM_WRITE_PROT 0x171
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#define SWIM_TRACK_ZERO 0x172
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#define SWIM_TACHO 0x173
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#define SWIM_READ_DATA_1 0x174
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#define SWIM_MFM_MODE 0x175
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#define SWIM_SEEK_COMPLETE 0x176
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#define SWIM_ONEMEG_MEDIA 0x177
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/* Bits in handshake register */
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#define SWIM_MARK_BYTE 0x01
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#define SWIM_CRC_ZERO 0x02
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#define SWIM_RDDATA 0x04
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#define SWIM_SENSE 0x08
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#define SWIM_MOTEN 0x10
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#define SWIM_ERROR 0x20
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#define SWIM_DAT2BYTE 0x40
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#define SWIM_DAT1BYTE 0x80
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/* bits in setup register */
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#define SWIM_S_INV_WDATA 0x01
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#define SWIM_S_3_5_SELECT 0x02
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#define SWIM_S_GCR 0x04
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#define SWIM_S_FCLK_DIV2 0x08
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#define SWIM_S_ERROR_CORR 0x10
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#define SWIM_S_IBM_DRIVE 0x20
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#define SWIM_S_GCR_WRITE 0x40
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#define SWIM_S_TIMEOUT 0x80
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/* bits in mode register */
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#define SWIM_CLFIFO 0x01
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#define SWIM_ENBL1 0x02
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#define SWIM_ENBL2 0x04
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#define SWIM_ACTION 0x08
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#define SWIM_WRITE_MODE 0x10
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#define SWIM_HEDSEL 0x20
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#define SWIM_MOTON 0x80
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static void fd_recalibrate(FDrive *drive)
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{
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}
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static void swim_change_cb(void *opaque, bool load, Error **errp)
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{
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FDrive *drive = opaque;
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if (!load) {
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blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
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} else {
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if (!blkconf_apply_backend_options(drive->conf,
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blk_is_read_only(drive->blk), false,
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errp)) {
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return;
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}
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}
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}
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static const BlockDevOps swim_block_ops = {
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.change_media_cb = swim_change_cb,
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};
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static Property swim_drive_properties[] = {
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DEFINE_PROP_INT32("unit", SWIMDrive, unit, -1),
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DEFINE_BLOCK_PROPERTIES(SWIMDrive, conf),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void swim_drive_realize(DeviceState *qdev, Error **errp)
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{
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SWIMDrive *dev = SWIM_DRIVE(qdev);
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SWIMBus *bus = SWIM_BUS(qdev->parent_bus);
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FDrive *drive;
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int ret;
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if (dev->unit == -1) {
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for (dev->unit = 0; dev->unit < SWIM_MAX_FD; dev->unit++) {
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drive = &bus->ctrl->drives[dev->unit];
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if (!drive->blk) {
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break;
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}
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}
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}
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if (dev->unit >= SWIM_MAX_FD) {
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error_setg(errp, "Can't create floppy unit %d, bus supports "
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"only %d units", dev->unit, SWIM_MAX_FD);
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return;
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}
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drive = &bus->ctrl->drives[dev->unit];
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if (drive->blk) {
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error_setg(errp, "Floppy unit %d is in use", dev->unit);
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return;
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}
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if (!dev->conf.blk) {
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/* Anonymous BlockBackend for an empty drive */
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dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL);
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ret = blk_attach_dev(dev->conf.blk, qdev);
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assert(ret == 0);
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}
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if (!blkconf_blocksizes(&dev->conf, errp)) {
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return;
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}
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if (dev->conf.logical_block_size != 512 ||
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dev->conf.physical_block_size != 512)
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{
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error_setg(errp, "Physical and logical block size must "
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"be 512 for floppy");
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return;
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}
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/*
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* rerror/werror aren't supported by fdc and therefore not even registered
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* with qdev. So set the defaults manually before they are used in
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* blkconf_apply_backend_options().
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*/
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dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
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dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
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if (!blkconf_apply_backend_options(&dev->conf,
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blk_is_read_only(dev->conf.blk),
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false, errp)) {
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return;
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}
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/*
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* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
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* for empty drives.
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*/
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if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
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blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
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error_setg(errp, "fdc doesn't support drive option werror");
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return;
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}
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if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
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error_setg(errp, "fdc doesn't support drive option rerror");
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return;
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}
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drive->conf = &dev->conf;
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drive->blk = dev->conf.blk;
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drive->swimctrl = bus->ctrl;
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blk_set_dev_ops(drive->blk, &swim_block_ops, drive);
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}
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static void swim_drive_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *k = DEVICE_CLASS(klass);
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k->realize = swim_drive_realize;
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set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
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k->bus_type = TYPE_SWIM_BUS;
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device_class_set_props(k, swim_drive_properties);
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k->desc = "virtual SWIM drive";
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}
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static const TypeInfo swim_drive_info = {
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.name = TYPE_SWIM_DRIVE,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(SWIMDrive),
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.class_init = swim_drive_class_init,
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};
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static const TypeInfo swim_bus_info = {
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.name = TYPE_SWIM_BUS,
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.parent = TYPE_BUS,
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.instance_size = sizeof(SWIMBus),
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};
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static void iwmctrl_write(void *opaque, hwaddr reg, uint64_t value,
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unsigned size)
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{
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SWIMCtrl *swimctrl = opaque;
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reg >>= REG_SHIFT;
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swimctrl->regs[reg >> 1] = reg & 1;
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if (swimctrl->regs[IWM_Q6] &&
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swimctrl->regs[IWM_Q7]) {
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if (swimctrl->regs[IWM_MTR]) {
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/* data register */
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swimctrl->iwm_data = value;
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} else {
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/* mode register */
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swimctrl->iwm_mode = value;
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/* detect sequence to switch from IWM mode to SWIM mode */
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switch (swimctrl->iwm_switch) {
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case 0:
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if (value == 0x57) {
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swimctrl->iwm_switch++;
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}
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break;
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case 1:
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if (value == 0x17) {
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swimctrl->iwm_switch++;
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}
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break;
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case 2:
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if (value == 0x57) {
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swimctrl->iwm_switch++;
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}
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break;
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case 3:
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if (value == 0x57) {
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swimctrl->mode = SWIM_MODE_SWIM;
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swimctrl->iwm_switch = 0;
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}
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break;
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}
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}
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}
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}
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static uint64_t iwmctrl_read(void *opaque, hwaddr reg, unsigned size)
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{
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SWIMCtrl *swimctrl = opaque;
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reg >>= REG_SHIFT;
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swimctrl->regs[reg >> 1] = reg & 1;
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return 0;
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}
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static void swimctrl_write(void *opaque, hwaddr reg, uint64_t value,
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unsigned size)
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{
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SWIMCtrl *swimctrl = opaque;
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if (swimctrl->mode == SWIM_MODE_IWM) {
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iwmctrl_write(opaque, reg, value, size);
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return;
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}
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reg >>= REG_SHIFT;
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switch (reg) {
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case SWIM_WRITE_PHASE:
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swimctrl->swim_phase = value;
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break;
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case SWIM_WRITE_MODE0:
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swimctrl->swim_mode &= ~value;
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break;
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case SWIM_WRITE_MODE1:
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swimctrl->swim_mode |= value;
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break;
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case SWIM_WRITE_DATA:
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case SWIM_WRITE_MARK:
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case SWIM_WRITE_CRC:
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case SWIM_WRITE_PARAMETER:
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case SWIM_WRITE_SETUP:
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break;
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}
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}
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static uint64_t swimctrl_read(void *opaque, hwaddr reg, unsigned size)
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{
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SWIMCtrl *swimctrl = opaque;
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uint32_t value = 0;
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if (swimctrl->mode == SWIM_MODE_IWM) {
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return iwmctrl_read(opaque, reg, size);
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}
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reg >>= REG_SHIFT;
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switch (reg) {
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case SWIM_READ_PHASE:
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value = swimctrl->swim_phase;
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break;
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case SWIM_READ_HANDSHAKE:
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if (swimctrl->swim_phase == SWIM_DRIVE_PRESENT) {
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/* always answer "no drive present" */
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value = SWIM_SENSE;
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}
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break;
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case SWIM_READ_DATA:
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case SWIM_READ_MARK:
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case SWIM_READ_ERROR:
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case SWIM_READ_PARAMETER:
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case SWIM_READ_SETUP:
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case SWIM_READ_STATUS:
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break;
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}
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return value;
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}
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static const MemoryRegionOps swimctrl_mem_ops = {
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.write = swimctrl_write,
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.read = swimctrl_read,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void sysbus_swim_reset(DeviceState *d)
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{
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SWIM *sys = SWIM(d);
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SWIMCtrl *ctrl = &sys->ctrl;
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int i;
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ctrl->mode = 0;
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ctrl->iwm_switch = 0;
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for (i = 0; i < 8; i++) {
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ctrl->regs[i] = 0;
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}
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ctrl->iwm_data = 0;
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ctrl->iwm_mode = 0;
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ctrl->swim_phase = 0;
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ctrl->swim_mode = 0;
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for (i = 0; i < SWIM_MAX_FD; i++) {
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fd_recalibrate(&ctrl->drives[i]);
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}
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}
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static void sysbus_swim_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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SWIM *sbs = SWIM(obj);
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SWIMCtrl *swimctrl = &sbs->ctrl;
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memory_region_init_io(&swimctrl->iomem, obj, &swimctrl_mem_ops, swimctrl,
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"swim", 0x2000);
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sysbus_init_mmio(sbd, &swimctrl->iomem);
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}
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static void sysbus_swim_realize(DeviceState *dev, Error **errp)
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{
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SWIM *sys = SWIM(dev);
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SWIMCtrl *swimctrl = &sys->ctrl;
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qbus_create_inplace(&swimctrl->bus, sizeof(SWIMBus), TYPE_SWIM_BUS, dev,
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NULL);
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swimctrl->bus.ctrl = swimctrl;
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}
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static const VMStateDescription vmstate_fdrive = {
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.name = "fdrive",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_swim = {
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.name = "swim",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(mode, SWIMCtrl),
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/* IWM mode */
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VMSTATE_INT32(iwm_switch, SWIMCtrl),
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VMSTATE_UINT16_ARRAY(regs, SWIMCtrl, 8),
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VMSTATE_UINT8(iwm_data, SWIMCtrl),
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VMSTATE_UINT8(iwm_mode, SWIMCtrl),
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/* SWIM mode */
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VMSTATE_UINT8(swim_phase, SWIMCtrl),
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VMSTATE_UINT8(swim_mode, SWIMCtrl),
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/* Drives */
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VMSTATE_STRUCT_ARRAY(drives, SWIMCtrl, SWIM_MAX_FD, 1,
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vmstate_fdrive, FDrive),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_sysbus_swim = {
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.name = "SWIM",
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT(ctrl, SWIM, 0, vmstate_swim, SWIMCtrl),
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VMSTATE_END_OF_LIST()
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}
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};
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static void sysbus_swim_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = sysbus_swim_realize;
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dc->reset = sysbus_swim_reset;
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dc->vmsd = &vmstate_sysbus_swim;
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}
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static const TypeInfo sysbus_swim_info = {
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.name = TYPE_SWIM,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SWIM),
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.instance_init = sysbus_swim_init,
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.class_init = sysbus_swim_class_init,
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};
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static void swim_register_types(void)
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{
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type_register_static(&sysbus_swim_info);
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type_register_static(&swim_bus_info);
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type_register_static(&swim_drive_info);
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}
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type_init(swim_register_types)
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