2017-01-11 15:07:08 +01:00
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/*
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2017-10-25 13:39:20 +02:00
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* Licensed under the GNU General Public License version 2 with exceptions. See
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* LICENSE file in the project root for full license information
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2017-01-11 15:07:08 +01:00
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*/
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/** \file
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* \brief
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* ESC hardware layer functions for LAN9252.
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*
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* Function to read and write commands to the ESC. Used to read/write ESC
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* registers and memory.
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*/
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#include "esc.h"
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#include <spi/spi.h>
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#include <string.h>
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#include <gpio.h>
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#define ESC_CMD_SERIAL_WRITE 0x02
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#define ESC_CMD_SERIAL_READ 0x03
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#define ESC_CMD_FAST_READ 0x0B
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#define ESC_CMD_RESET_SQI 0xFF
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#define ESC_CMD_FAST_READ_DUMMY 1
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#define ESC_CMD_ADDR_INC BIT(6)
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#define ESC_PRAM_RD_FIFO_REG 0x000
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#define ESC_PRAM_WR_FIFO_REG 0x020
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#define ESC_PRAM_RD_ADDR_LEN_REG 0x308
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#define ESC_PRAM_RD_CMD_REG 0x30C
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#define ESC_PRAM_WR_ADDR_LEN_REG 0x310
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#define ESC_PRAM_WR_CMD_REG 0x314
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#define ESC_PRAM_CMD_BUSY BIT(31)
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#define ESC_PRAM_CMD_ABORT BIT(30)
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#define ESC_PRAM_CMD_CNT(x) ((x >> 8) & 0x1F)
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#define ESC_PRAM_CMD_AVAIL BIT(0)
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#define ESC_PRAM_SIZE(x) ((x) << 16)
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#define ESC_PRAM_ADDR(x) ((x) << 0)
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#define ESC_CSR_DATA_REG 0x300
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#define ESC_CSR_CMD_REG 0x304
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#define ESC_CSR_CMD_BUSY BIT(31)
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#define ESC_CSR_CMD_READ (BIT(31) | BIT(30))
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#define ESC_CSR_CMD_WRITE BIT(31)
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#define ESC_CSR_CMD_SIZE(x) (x << 16)
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#define ESC_RESET_CTRL_REG 0x1F8
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#define ESC_RESET_CTRL_RST BIT(6)
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static int lan9252 = -1;
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/* lan9252 singel write */
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static void lan9252_write_32 (uint16_t address, uint32_t val)
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{
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uint8_t data[7];
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data[0] = ESC_CMD_SERIAL_WRITE;
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data[1] = ((address >> 8) & 0xFF);
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data[2] = (address & 0xFF);
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data[3] = (val & 0xFF);
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data[4] = ((val >> 8) & 0xFF);
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data[5] = ((val >> 16) & 0xFF);
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data[6] = ((val >> 24) & 0xFF);
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/* Select device. */
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spi_select (lan9252);
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/* Write data */
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write (lan9252, data, sizeof(data));
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/* Un-select device. */
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spi_unselect (lan9252);
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}
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/* lan9252 single read */
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static uint32_t lan9252_read_32 (uint32_t address)
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{
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uint8_t data[4];
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uint8_t result[4];
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data[0] = ESC_CMD_FAST_READ;
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data[1] = ((address >> 8) & 0xFF);
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data[2] = (address & 0xFF);
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data[3] = ESC_CMD_FAST_READ_DUMMY;
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/* Select device. */
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spi_select (lan9252);
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/* Read data */
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write (lan9252, data, sizeof(data));
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read (lan9252, result, sizeof(result));
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/* Un-select device. */
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spi_unselect (lan9252);
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return ((result[3] << 24) |
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(result[2] << 16) |
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(result[1] << 8) |
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result[0]);
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}
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/* ESC read CSR function */
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static void ESC_read_csr (uint16_t address, void *buf, uint16_t len)
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{
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uint32_t value;
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value = (ESC_CSR_CMD_READ | ESC_CSR_CMD_SIZE(len) | address);
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lan9252_write_32(ESC_CSR_CMD_REG, value);
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do
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{
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value = lan9252_read_32(ESC_CSR_CMD_REG);
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} while(value & ESC_CSR_CMD_BUSY);
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value = lan9252_read_32(ESC_CSR_DATA_REG);
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memcpy(buf, (uint8_t *)&value, len);
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}
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/* ESC write CSR function */
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static void ESC_write_csr (uint16_t address, void *buf, uint16_t len)
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{
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uint32_t value;
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memcpy((uint8_t*)&value, buf,len);
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lan9252_write_32(ESC_CSR_DATA_REG, value);
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value = (ESC_CSR_CMD_WRITE | ESC_CSR_CMD_SIZE(len) | address);
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lan9252_write_32(ESC_CSR_CMD_REG, value);
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do
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{
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value = lan9252_read_32(ESC_CSR_CMD_REG);
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} while(value & ESC_CSR_CMD_BUSY);
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}
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/* ESC read process data ram function */
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static void ESC_read_pram (uint16_t address, void *buf, uint16_t len)
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{
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uint32_t value;
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uint8_t * temp_buf = buf;
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2017-08-30 10:18:39 +02:00
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uint16_t byte_offset = 0;
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2017-01-11 15:07:08 +01:00
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uint8_t fifo_cnt, first_byte_position, temp_len, data[4];
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value = ESC_PRAM_CMD_ABORT;
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lan9252_write_32(ESC_PRAM_RD_CMD_REG, value);
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do
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{
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value = lan9252_read_32(ESC_PRAM_RD_CMD_REG);
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}while(value & ESC_PRAM_CMD_BUSY);
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value = ESC_PRAM_SIZE(len) | ESC_PRAM_ADDR(address);
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lan9252_write_32(ESC_PRAM_RD_ADDR_LEN_REG, value);
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value = ESC_PRAM_CMD_BUSY;
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lan9252_write_32(ESC_PRAM_RD_CMD_REG, value);
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do
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{
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value = lan9252_read_32(ESC_PRAM_RD_CMD_REG);
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}while((value & ESC_PRAM_CMD_AVAIL) == 0);
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/* Fifo count */
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fifo_cnt = ESC_PRAM_CMD_CNT(value);
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/* Read first value from FIFO */
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value = lan9252_read_32(ESC_PRAM_RD_FIFO_REG);
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fifo_cnt--;
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/* Find out first byte position and adjust the copy from that
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* according to LAN9252 datasheet and MicroChip SDK code
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*/
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first_byte_position = (address & 0x03);
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temp_len = ((4 - first_byte_position) > len) ? len : (4 - first_byte_position);
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memcpy(temp_buf ,((uint8_t *)&value + first_byte_position), temp_len);
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len -= temp_len;
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byte_offset += temp_len;
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/* Select device. */
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spi_select (lan9252);
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/* Send command and address for fifo read */
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data[0] = ESC_CMD_FAST_READ;
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data[1] = ((ESC_PRAM_RD_FIFO_REG >> 8) & 0xFF);
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data[2] = (ESC_PRAM_RD_FIFO_REG & 0xFF);
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data[3] = ESC_CMD_FAST_READ_DUMMY;
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write (lan9252, data, sizeof(data));
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/* Continue reading until we have read len */
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while(len > 0)
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{
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temp_len = (len > 4) ? 4: len;
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/* Always read 4 byte */
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read (lan9252, (temp_buf + byte_offset), sizeof(uint32_t));
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fifo_cnt--;
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len -= temp_len;
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byte_offset += temp_len;
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}
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/* Un-select device. */
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spi_unselect (lan9252);
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}
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/* ESC write process data ram function */
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static void ESC_write_pram (uint16_t address, void *buf, uint16_t len)
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{
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uint32_t value;
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uint8_t * temp_buf = buf;
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2017-08-30 10:18:39 +02:00
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uint16_t byte_offset = 0;
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2017-01-11 15:07:08 +01:00
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uint8_t fifo_cnt, first_byte_position, temp_len, data[3];
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value = ESC_PRAM_CMD_ABORT;
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lan9252_write_32(ESC_PRAM_WR_CMD_REG, value);
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do
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{
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value = lan9252_read_32(ESC_PRAM_WR_CMD_REG);
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}while(value & ESC_PRAM_CMD_BUSY);
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value = ESC_PRAM_SIZE(len) | ESC_PRAM_ADDR(address);
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lan9252_write_32(ESC_PRAM_WR_ADDR_LEN_REG, value);
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value = ESC_PRAM_CMD_BUSY;
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lan9252_write_32(ESC_PRAM_WR_CMD_REG, value);
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do
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{
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value = lan9252_read_32(ESC_PRAM_WR_CMD_REG);
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}while((value & ESC_PRAM_CMD_AVAIL) == 0);
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/* Fifo count */
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fifo_cnt = ESC_PRAM_CMD_CNT(value);
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/* Find out first byte position and adjust the copy from that
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* according to LAN9252 datasheet
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*/
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first_byte_position = (address & 0x03);
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temp_len = ((4 - first_byte_position) > len) ? len : (4 - first_byte_position);
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memcpy(((uint8_t *)&value + first_byte_position), temp_buf, temp_len);
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/* Write first value from FIFO */
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lan9252_write_32(ESC_PRAM_WR_FIFO_REG, value);
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len -= temp_len;
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byte_offset += temp_len;
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fifo_cnt--;
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/* Select device. */
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spi_select (lan9252);
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/* Send command and address for incrementing write */
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data[0] = ESC_CMD_SERIAL_WRITE;
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data[1] = ((ESC_PRAM_WR_FIFO_REG >> 8) & 0xFF);
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data[2] = (ESC_PRAM_WR_FIFO_REG & 0xFF);
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write (lan9252, data, sizeof(data));
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/* Continue reading until we have read len */
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while(len > 0)
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{
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temp_len = (len > 4) ? 4 : len;
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value = 0;
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memcpy((uint8_t *)&value, (temp_buf + byte_offset), temp_len);
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/* Always write 4 byte */
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write (lan9252, (void *)&value, sizeof(value));
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fifo_cnt--;
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len -= temp_len;
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byte_offset += temp_len;
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}
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/* Un-select device. */
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spi_unselect (lan9252);
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}
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/** ESC read function used by the Slave stack.
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*
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* @param[in] address = address of ESC register to read
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* @param[out] buf = pointer to buffer to read in
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* @param[in] len = number of bytes to read
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*/
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void ESC_read (uint16_t address, void *buf, uint16_t len)
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{
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/* Select Read function depending on address, process data ram or not */
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if (address >= 0x1000)
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{
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ESC_read_pram(address, buf, len);
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}
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else
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{
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uint16_t size;
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uint8_t *temp_buf = (uint8_t *)buf;
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while(len > 0)
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{
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/* We write maximum 4 bytes at the time */
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size = (len > 4) ? 4 : len;
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/* Make size aligned to address according to LAN9252 datasheet
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* Table 12-14 EtherCAT CSR Address VS size and MicroChip SDK code
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*/
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/* If we got an odd address size is 1 , 01b 11b is captured */
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if(address & BIT(0))
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{
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size = 1;
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}
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/* If address 1xb and size != 1 and 3 , allow size 2 else size 1 */
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else if (address & BIT(1))
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{
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size = (size & BIT(0)) ? 1 : 2;
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}
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/* size 3 not valid */
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else if (size == 3)
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{
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size = 1;
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}
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/* else size is kept AS IS */
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ESC_read_csr(address, temp_buf, size);
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/* next address */
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len -= size;
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temp_buf += size;
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address += size;
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}
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}
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/* To mimic the ET1100 always providing AlEvent on every read or write */
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ESC_read_csr(ESCREG_ALEVENT,(void *)&ESCvar.ALevent,sizeof(ESCvar.ALevent));
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ESCvar.ALevent = etohs (ESCvar.ALevent);
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}
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/** ESC write function used by the Slave stack.
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*
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* @param[in] address = address of ESC register to write
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* @param[out] buf = pointer to buffer to write from
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* @param[in] len = number of bytes to write
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*/
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void ESC_write (uint16_t address, void *buf, uint16_t len)
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{
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/* Select Write function depending on address, process data ram or not */
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if (address >= 0x1000)
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{
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ESC_write_pram(address, buf, len);
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}
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else
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{
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uint16_t size;
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uint8_t *temp_buf = (uint8_t *)buf;
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while(len > 0)
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{
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/* We write maximum 4 bytes at the time */
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size = (len > 4) ? 4 : len;
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/* Make size aligned to address according to LAN9252 datasheet
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* Table 12-14 EtherCAT CSR Address VS size and MicroChip SDK code
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*/
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/* If we got an odd address size is 1 , 01b 11b is captured */
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if(address & BIT(0))
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{
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size = 1;
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}
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/* If address 1xb and size != 1 and 3 , allow size 2 else size 1 */
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else if (address & BIT(1))
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|
|
{
|
|
|
|
size = (size & BIT(0)) ? 1 : 2;
|
|
|
|
}
|
|
|
|
/* size 3 not valid */
|
|
|
|
else if (size == 3)
|
|
|
|
{
|
|
|
|
size = 1;
|
|
|
|
}
|
|
|
|
/* else size is kept AS IS */
|
|
|
|
ESC_write_csr(address, temp_buf, size);
|
|
|
|
|
|
|
|
/* next address */
|
|
|
|
len -= size;
|
|
|
|
temp_buf += size;
|
|
|
|
address += size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* To mimic the ET1x00 always providing AlEvent on every read or write */
|
|
|
|
ESC_read_csr(ESCREG_ALEVENT,(void *)&ESCvar.ALevent,sizeof(ESCvar.ALevent));
|
|
|
|
ESCvar.ALevent = etohs (ESCvar.ALevent);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Un-used due to evb-lan9252-digio not havning any possability to
|
|
|
|
* reset except over SPI.
|
|
|
|
*/
|
|
|
|
void ESC_reset (void)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2017-10-25 20:28:13 +02:00
|
|
|
void ESC_init (const esc_cfg_t * config)
|
2017-01-11 15:07:08 +01:00
|
|
|
{
|
|
|
|
uint32_t value;
|
2017-10-25 20:28:13 +02:00
|
|
|
const char * spi_name = (char *)config->user_arg;
|
2017-01-11 15:07:08 +01:00
|
|
|
lan9252 = open (spi_name, O_RDWR, 0);
|
|
|
|
|
|
|
|
/* Reset the ecat core here due to evb-lan9252-digio not having any GPIO
|
|
|
|
* for that purpose.
|
|
|
|
*/
|
|
|
|
lan9252_write_32(ESC_RESET_CTRL_REG,ESC_RESET_CTRL_RST);
|
|
|
|
do
|
|
|
|
{
|
|
|
|
value = lan9252_read_32(ESC_CSR_CMD_REG);
|
|
|
|
} while(value & ESC_RESET_CTRL_RST);
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
}
|