2016-08-26 17:42:35 +02:00
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/*
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* SOES Simple Open EtherCAT Slave
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*
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* File : esc_hw.c
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* Version : 0.9.2
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* Date : 22-02-2010
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* Copyright (C) 2007-2013 Arthur Ketels
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* Copyright (C) 2012-2013 rt-labs
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*
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* SOES is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the Free
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* Software Foundation.
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*
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* SOES is distributed in the hope that it will be useful, but WITHOUT ANY
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* WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* As a special exception, if other files instantiate templates or use macros
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* or inline functions from this file, or you compile this file and link it
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* with other works to produce a work based on this file, this file does not
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* by itself cause the resulting work to be covered by the GNU General Public
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* License. However the source code for this file must still be made available
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* in accordance with section (3) of the GNU General Public License.
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*
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* This exception does not invalidate any other reasons why a work based on
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* this file might be covered by the GNU General Public License.
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*
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* The EtherCAT Technology, the trade name and logo "EtherCAT" are the intellectual
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* property of, and protected by Beckhoff Automation GmbH.
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*/
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/** \file
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* \brief
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* ESC hardware layer functions.
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*
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* Function to read and write commands to the ESC. Used to read/write ESC
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* registers and memory.
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*/
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#include "esc.h"
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#include "esc_eep.h"
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#include "xmc_gpio.h"
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#include "xmc_ecat.h"
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2017-01-20 14:34:38 +01:00
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#ifdef XMC4800_F144x2048
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2016-08-26 17:42:35 +02:00
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/* ESC to PHY interconnect setup */
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2017-01-20 14:34:38 +01:00
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/* PHY management interface signal definitions*/
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#define ECAT_MDO P0_12
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#define ECAT_MCLK P3_3
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#define ECAT_PORT_CTRL_LATCHIN0 XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5
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#define ECAT_PORT_CTRL_LATCHIN1 XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4
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#define ECAT_PHYADDR_OFFSET 0
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/* EtherCAT slave physical layer pin configurations */
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#define ECAT_CLK25 P6_0
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#define ECAT_PHY_RESET P0_0
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#define ECAT_LED_RUN P0_8
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#define ECAT_LED_ERR P0_7
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/* EtherCAT slave physical layer Port 0 pin configurations */
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#define ECAT_P0_LINK_STATUS P1_15
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#define ECAT_P0_LED_LINK_ACT P6_3
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#define ECAT_P0_RXD3 P5_7
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#define ECAT_P0_RXD2 P5_2
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#define ECAT_P0_RXD1 P5_1
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#define ECAT_P0_RXD0 P5_0
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#define ECAT_P0_RX_DV P5_6
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#define ECAT_P0_RX_CLK P5_4
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#define ECAT_P0_RX_ERR P2_6
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#define ECAT_P0_TXD3 P6_6
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#define ECAT_P0_TXD2 P6_5
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#define ECAT_P0_TXD1 P6_4
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#define ECAT_P0_TXD0 P6_2
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#define ECAT_P0_TX_EN P6_1
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#define ECAT_P0_TX_CLK P5_5
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/* EtherCAT slave physical layer Port 1 pin configurations */
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#define ECAT_P1_LINK_STATUS P3_4
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#define ECAT_P1_LED_LINK_ACT P3_12
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#define ECAT_P1_RXD3 P0_4
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#define ECAT_P1_RXD2 P0_5
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#define ECAT_P1_RXD1 P0_6
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#define ECAT_P1_RXD0 P0_11
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#define ECAT_P1_RX_DV P0_9
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#define ECAT_P1_RX_CLK P0_1
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#define ECAT_P1_RX_ERR P15_2
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#define ECAT_P1_TXD3 P0_3
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#define ECAT_P1_TXD2 P0_2
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#define ECAT_P1_TXD1 P3_2
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#define ECAT_P1_TXD0 P3_1
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#define ECAT_P1_TX_EN P3_0
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#define ECAT_P1_TX_CLK P0_10
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/* configure outputs */
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#define AF_ECAT0_P0_TXD3 P6_6_AF_ECAT0_P0_TXD3
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#define AF_ECAT0_P0_TXD2 P6_5_AF_ECAT0_P0_TXD2
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#define AF_ECAT0_P0_TXD1 P6_4_AF_ECAT0_P0_TXD1
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#define AF_ECAT0_P0_TXD0 P6_2_AF_ECAT0_P0_TXD0
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#define AF_ECAT0_P0_TX_EN P6_1_AF_ECAT0_P0_TX_ENA
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#define AF_ECAT0_P1_TXD3 P0_3_AF_ECAT0_P1_TXD3
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#define AF_ECAT0_P1_TXD2 P0_2_AF_ECAT0_P1_TXD2
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#define AF_ECAT0_P1_TXD1 P3_2_AF_ECAT0_P1_TXD1
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#define AF_ECAT0_P1_TXD0 P3_1_AF_ECAT0_P1_TXD0
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#define AF_ECAT0_P1_TX_EN P3_0_AF_ECAT0_P1_TX_ENA
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#define AF_ECAT0_CLK25 P6_0_AF_ECAT0_PHY_CLK25
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#define AF_ECAT0_MCLK P3_3_AF_ECAT0_MCLK
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#define AF_ECAT0_P0_LED_LINK_ACT P6_3_AF_ECAT0_P0_LED_LINK_ACT
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#define AF_ECAT0_P1_LED_LINK_ACT P3_12_AF_ECAT0_P1_LED_LINK_ACT
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#define AF_ECAT0_LED_RUN P0_8_AF_ECAT0_LED_RUN
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#define AF_ECAT0_LED_ERR P0_7_AF_ECAT0_LED_ERR
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#define AF_ECAT0_MDO P0_12_HWCTRL_ECAT0_MDO
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#define AF_ECAT0_PHY_RESET P0_0_AF_ECAT0_PHY_RESET
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#define ECAT_PORT_CTRL_MDIO XMC_ECAT_PORT_CTRL_MDIO_P0_12
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#define ECAT_PORT0_CTRL_RXD0 XMC_ECAT_PORT0_CTRL_RXD0_P5_0
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#define ECAT_PORT0_CTRL_RXD1 XMC_ECAT_PORT0_CTRL_RXD1_P5_1
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#define ECAT_PORT0_CTRL_RXD2 XMC_ECAT_PORT0_CTRL_RXD2_P5_2
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#define ECAT_PORT0_CTRL_RXD3 XMC_ECAT_PORT0_CTRL_RXD3_P5_7
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#define ECAT_PORT0_CTRL_RX_CLK XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4
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#define ECAT_PORT0_CTRL_RX_DV XMC_ECAT_PORT0_CTRL_RX_DV_P5_6
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#define ECAT_PORT0_CTRL_RX_ERR XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6
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#define ECAT_PORT0_CTRL_LINK XMC_ECAT_PORT0_CTRL_LINK_P1_15
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#define ECAT_PORT0_CTRL_TX_CLK XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5
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#define ECAT_PORT0_CTRL_TX_SHIFT XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS
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#define ECAT_PORT1_CTRL_RXD0 XMC_ECAT_PORT1_CTRL_RXD0_P0_11
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#define ECAT_PORT1_CTRL_RXD1 XMC_ECAT_PORT1_CTRL_RXD1_P0_6
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#define ECAT_PORT1_CTRL_RXD2 XMC_ECAT_PORT1_CTRL_RXD2_P0_5
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#define ECAT_PORT1_CTRL_RXD3 XMC_ECAT_PORT1_CTRL_RXD3_P0_4
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#define ECAT_PORT1_CTRL_RX_CLK XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1
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#define ECAT_PORT1_CTRL_RX_DV XMC_ECAT_PORT1_CTRL_RX_DV_P0_9
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#define ECAT_PORT1_CTRL_RX_ERR XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2
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#define ECAT_PORT1_CTRL_LINK XMC_ECAT_PORT1_CTRL_LINK_P3_4
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#define ECAT_PORT1_CTRL_TX_CLK XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10
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#define ECAT_PORT1_CTRL_TX_SHIFT XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS
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#endif
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#ifdef XMC4300_F100x256
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#define ECAT_MDO P0_12
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#define ECAT_MCLK P3_3
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#define ECAT_PORT_CTRL_LATCHIN0 XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5
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#define ECAT_PORT_CTRL_LATCHIN1 XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4
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#define ECAT_PHYADDR_OFFSET 0
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#define ECAT_CLK25 P1_13
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#define ECAT_PHY_RESET P2_10
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#define ECAT_LED_RUN P1_11
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#define ECAT_LED_ERR P1_10
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#define ECAT_P0_LINK_STATUS P1_15
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#define ECAT_P0_LED_LINK_ACT P1_12
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#define ECAT_P0_RXD3 P5_7
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#define ECAT_P0_RXD2 P5_2
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#define ECAT_P0_RXD1 P5_1
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#define ECAT_P0_RXD0 P1_4
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#define ECAT_P0_RX_DV P1_9
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#define ECAT_P0_RX_CLK P1_1
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#define ECAT_P0_RX_ERR P2_6
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#define ECAT_P0_TXD3 P1_2
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#define ECAT_P0_TXD2 P1_8
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#define ECAT_P0_TXD1 P1_7
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#define ECAT_P0_TXD0 P1_6
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#define ECAT_P0_TX_EN P1_3
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#define ECAT_P0_TX_CLK P1_0
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#define ECAT_P1_LINK_STATUS P15_3
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#define ECAT_P1_LED_LINK_ACT P0_11
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#define ECAT_P1_RXD3 P14_14
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#define ECAT_P1_RXD2 P14_13
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#define ECAT_P1_RXD1 P14_12
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#define ECAT_P1_RXD0 P14_7
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#define ECAT_P1_RX_DV P14_15
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#define ECAT_P1_RX_CLK P14_6
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#define ECAT_P1_RX_ERR P15_2
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#define ECAT_P1_TXD3 P0_3
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#define ECAT_P1_TXD2 P0_2
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#define ECAT_P1_TXD1 P3_2
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#define ECAT_P1_TXD0 P3_1
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#define ECAT_P1_TX_EN P3_0
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#define ECAT_P1_TX_CLK P0_10
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/* configure outputs */
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#define AF_ECAT0_P0_TXD3 P1_2_AF_ECAT0_P0_TXD3
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#define AF_ECAT0_P0_TXD2 P1_8_AF_ECAT0_P0_TXD2
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#define AF_ECAT0_P0_TXD1 P1_7_AF_ECAT0_P0_TXD1
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#define AF_ECAT0_P0_TXD0 P1_6_AF_ECAT0_P0_TXD0
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#define AF_ECAT0_P0_TX_EN P1_3_AF_ECAT0_P0_TX_ENA
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#define AF_ECAT0_P1_TXD3 P0_3_AF_ECAT0_P1_TXD3
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#define AF_ECAT0_P1_TXD2 P0_2_AF_ECAT0_P1_TXD2
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#define AF_ECAT0_P1_TXD1 P3_2_AF_ECAT0_P1_TXD1
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#define AF_ECAT0_P1_TXD0 P3_1_AF_ECAT0_P1_TXD0
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#define AF_ECAT0_P1_TX_EN P3_0_AF_ECAT0_P1_TX_ENA
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#define AF_ECAT0_CLK25 P1_13_AF_ECAT0_PHY_CLK25
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#define AF_ECAT0_MCLK P3_3_AF_ECAT0_MCLK
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#define AF_ECAT0_P0_LED_LINK_ACT P1_12_AF_ECAT0_P0_LED_LINK_ACT
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#define AF_ECAT0_P1_LED_LINK_ACT P0_11_AF_ECAT0_P1_LED_LINK_ACT
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#define AF_ECAT0_LED_RUN P1_11_AF_ECAT0_LED_RUN
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#define AF_ECAT0_LED_ERR P1_10_AF_ECAT0_LED_ERR
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#define AF_ECAT0_MDO P0_12_HWCTRL_ECAT0_MDO
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#define AF_ECAT0_PHY_RESET P2_10_AF_ECAT0_PHY_RESET
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#define ECAT_PORT_CTRL_MDIO XMC_ECAT_PORT_CTRL_MDIO_P0_12
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#define ECAT_PORT0_CTRL_RXD0 XMC_ECAT_PORT0_CTRL_RXD0_P1_4
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#define ECAT_PORT0_CTRL_RXD1 XMC_ECAT_PORT0_CTRL_RXD1_P5_1
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#define ECAT_PORT0_CTRL_RXD2 XMC_ECAT_PORT0_CTRL_RXD2_P5_2
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#define ECAT_PORT0_CTRL_RXD3 XMC_ECAT_PORT0_CTRL_RXD3_P5_7
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#define ECAT_PORT0_CTRL_RX_CLK XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1
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#define ECAT_PORT0_CTRL_RX_DV XMC_ECAT_PORT0_CTRL_RX_DV_P1_9
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#define ECAT_PORT0_CTRL_RX_ERR XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6
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#define ECAT_PORT0_CTRL_LINK XMC_ECAT_PORT0_CTRL_LINK_P1_15
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#define ECAT_PORT0_CTRL_TX_CLK XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0
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#define ECAT_PORT1_CTRL_RXD0 XMC_ECAT_PORT1_CTRL_RXD0_P14_7
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#define ECAT_PORT1_CTRL_RXD1 XMC_ECAT_PORT1_CTRL_RXD1_P14_12
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#define ECAT_PORT1_CTRL_RXD2 XMC_ECAT_PORT1_CTRL_RXD2_P14_13
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#define ECAT_PORT1_CTRL_RXD3 XMC_ECAT_PORT1_CTRL_RXD3_P14_14
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#define ECAT_PORT1_CTRL_RX_CLK XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6
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#define ECAT_PORT1_CTRL_RX_DV XMC_ECAT_PORT1_CTRL_RX_DV_P14_15
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#define ECAT_PORT1_CTRL_RX_ERR XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2
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#define ECAT_PORT1_CTRL_LINK XMC_ECAT_PORT1_CTRL_LINK_P15_3
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#define ECAT_PORT1_CTRL_TX_CLK XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10
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#endif
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#define ESCADDR(x) (((uint8_t *) ECAT0_BASE) + x)
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static const XMC_ECAT_PORT_CTRL_t port_control = {
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.common = {
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.mdio = ECAT_PORT_CTRL_MDIO
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},
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.port0 = {
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.rxd0 = ECAT_PORT0_CTRL_RXD0,
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.rxd1 = ECAT_PORT0_CTRL_RXD1,
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.rxd2 = ECAT_PORT0_CTRL_RXD2,
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.rxd3 = ECAT_PORT0_CTRL_RXD3,
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.rx_clk = ECAT_PORT0_CTRL_RX_CLK,
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.rx_dv = ECAT_PORT0_CTRL_RX_DV,
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.rx_err = ECAT_PORT0_CTRL_RX_ERR,
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.link = ECAT_PORT0_CTRL_LINK,
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.tx_clk = ECAT_PORT0_CTRL_TX_CLK
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},
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.port1 = {
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.rxd0 = ECAT_PORT1_CTRL_RXD0,
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.rxd1 = ECAT_PORT1_CTRL_RXD1,
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.rxd2 = ECAT_PORT1_CTRL_RXD2,
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.rxd3 = ECAT_PORT1_CTRL_RXD3,
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.rx_clk = ECAT_PORT1_CTRL_RX_CLK,
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.rx_dv = ECAT_PORT1_CTRL_RX_DV,
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.rx_err = ECAT_PORT1_CTRL_RX_ERR,
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.link = ECAT_PORT1_CTRL_LINK,
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.tx_clk = ECAT_PORT1_CTRL_TX_CLK
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}
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};
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static const XMC_GPIO_CONFIG_t gpio_config_input = {
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.mode = XMC_GPIO_MODE_INPUT_TRISTATE,
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.output_level = 0,
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.output_strength = 0
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};
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static void init_input(XMC_GPIO_PORT_t *const port, const uint8_t pin)
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{
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XMC_GPIO_Init(port, pin, &gpio_config_input);
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}
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static void init_output(XMC_GPIO_PORT_t *const port, const uint8_t pin,
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uint32_t function, XMC_GPIO_OUTPUT_STRENGTH_t strength)
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{
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XMC_GPIO_CONFIG_t config;
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config.mode = (XMC_GPIO_MODE_t)((uint32_t)XMC_GPIO_MODE_OUTPUT_PUSH_PULL | function);
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config.output_level = XMC_GPIO_OUTPUT_LEVEL_LOW;
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config.output_strength = strength;
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XMC_GPIO_Init(port, pin, &config);
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}
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#define init_output_sharp(pin, function) init_output(pin, function, XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE);
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#define init_output_soft(pin, function) init_output(pin, function, XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE);
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/** ESC read function used by the Slave stack.
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*
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* @param[in] address = address of ESC register to read
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* @param[out] buf = pointer to buffer to read in
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* @param[in] len = number of bytes to read
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*/
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void ESC_read (uint16_t address, void *buf, uint16_t len)
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{
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ESCvar.ALevent = etohs ((uint16_t)ECAT0->AL_EVENT_REQ);
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memcpy (buf, ESCADDR(address), len);
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}
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/** ESC write function used by the Slave stack.
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*
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* @param[in] address = address of ESC register to write
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* @param[out] buf = pointer to buffer to write from
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* @param[in] len = number of bytes to write
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*/
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void ESC_write (uint16_t address, void *buf, uint16_t len)
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{
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ESCvar.ALevent = etohs ((uint16_t)ECAT0->AL_EVENT_REQ);
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memcpy(ESCADDR(address), buf, len);
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}
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void ESC_reset (void)
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{
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/* disable ESC to force reset */
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XMC_ECAT_Disable();
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/* initialize EEPROM emulation */
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EEP_init();
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}
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void ESC_init (const void * arg)
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{
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XMC_ECAT_CONFIG_t ecat_config;
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/* configure inputs */
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init_input(ECAT_P0_LINK_STATUS);
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init_input(ECAT_P0_RXD3);
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init_input(ECAT_P0_RXD2);
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init_input(ECAT_P0_RXD1);
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init_input(ECAT_P0_RXD0);
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init_input(ECAT_P0_RX_DV);
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init_input(ECAT_P0_RX_CLK);
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init_input(ECAT_P0_RX_ERR);
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init_input(ECAT_P0_TX_CLK);
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init_input(ECAT_P1_LINK_STATUS);
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init_input(ECAT_P1_RXD3);
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init_input(ECAT_P1_RXD2);
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init_input(ECAT_P1_RXD1);
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init_input(ECAT_P1_RXD0);
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init_input(ECAT_P1_RX_DV);
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init_input(ECAT_P1_RX_CLK);
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init_input(ECAT_P1_RX_ERR);
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init_input(ECAT_P1_TX_CLK);
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init_input(ECAT_MDO);
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XMC_ECAT_SetPortControl(port_control);
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/* read config from emulated EEPROM */
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memset(&ecat_config, 0, sizeof(XMC_ECAT_CONFIG_t));
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EEP_read (0, (uint8_t *) &ecat_config, sizeof(XMC_ECAT_CONFIG_t));
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XMC_ECAT_Init(&ecat_config);
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/* configure outputs */
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2017-01-20 14:34:38 +01:00
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init_output_sharp(ECAT_P0_TXD3, AF_ECAT0_P0_TXD3);
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init_output_sharp(ECAT_P0_TXD2, AF_ECAT0_P0_TXD2);
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init_output_sharp(ECAT_P0_TXD1, AF_ECAT0_P0_TXD1);
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init_output_sharp(ECAT_P0_TXD0, AF_ECAT0_P0_TXD0);
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init_output_sharp(ECAT_P0_TX_EN, AF_ECAT0_P0_TX_EN);
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init_output_sharp(ECAT_P1_TXD3, AF_ECAT0_P1_TXD3);
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init_output_sharp(ECAT_P1_TXD2, AF_ECAT0_P1_TXD2);
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init_output_sharp(ECAT_P1_TXD1, AF_ECAT0_P1_TXD1);
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init_output_sharp(ECAT_P1_TXD0, AF_ECAT0_P1_TXD0);
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init_output_sharp(ECAT_P1_TX_EN, AF_ECAT0_P1_TX_EN);
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init_output_sharp(ECAT_CLK25, AF_ECAT0_CLK25);
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init_output_sharp(ECAT_MCLK, AF_ECAT0_MCLK);
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init_output_soft(ECAT_P0_LED_LINK_ACT, AF_ECAT0_P0_LED_LINK_ACT);
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init_output_soft(ECAT_P1_LED_LINK_ACT, AF_ECAT0_P1_LED_LINK_ACT);
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init_output_soft(ECAT_LED_RUN, AF_ECAT0_LED_RUN);
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init_output_soft(ECAT_LED_ERR, AF_ECAT0_LED_ERR);
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init_input(ECAT_MDO);
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XMC_GPIO_SetHardwareControl(ECAT_MDO, AF_ECAT0_MDO);
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init_output_soft(ECAT_PHY_RESET, AF_ECAT0_PHY_RESET);
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2016-08-26 17:42:35 +02:00
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}
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