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Merge pull request #16 from nakarlsson/master 

Add support for XMC4800
pull/18/merge
Hans-Erik Floryd 2017-03-31 17:42:26 +02:00 committed by GitHub
parent 56bd0169b7 98a5106683
commit c020d4ba4a
4 changed files with 264 additions and 107 deletions
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10
applications/xmc4300_slavedemo/sii_eeprom.h
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@ -1,10 +0,0 @@
#ifndef _sii_eeprom_h_
#define _sii_eeprom_h_
extern const uint8_t _binary_sii_eeprom_bin_start;
extern const uint8_t _binary_sii_eeprom_bin_end;
#define SII_EE_DEFLT (&_binary_sii_eeprom_bin_start)
#define SII_EE_DEFLT_SIZE (&_binary_sii_eeprom_bin_end - &_binary_sii_eeprom_bin_start)
#endif

294
soes/hal/xmc4/esc_hw.c
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@ -44,74 +44,221 @@
#include "xmc_gpio.h"
#include "xmc_ecat.h"
#ifdef XMC4800_F144x2048
/* ESC to PHY interconnect setup */
/* PHY management interface signal definitions*/
#define ECAT_MDO P0_12
#define ECAT_MCLK P3_3
#define ECAT_MDO P0_12
#define ECAT_MCLK P3_3
#define ECAT_CLK25 P1_13
#define ECAT_PHY_RESET P2_10
#define ECAT_LED_RUN P1_11
#define ECAT_LED_ERR P1_10
#define ECAT_PORT_CTRL_LATCHIN0 XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5
#define ECAT_PORT_CTRL_LATCHIN1 XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4
#define ECAT_PHYADDR_OFFSET 0
#define ECAT_P0_LINK_STATUS P1_15
#define ECAT_P0_LED_LINK_ACT P1_12
#define ECAT_P0_RXD3 P5_7
#define ECAT_P0_RXD2 P5_2
#define ECAT_P0_RXD1 P5_1
#define ECAT_P0_RXD0 P1_4
#define ECAT_P0_RX_DV P1_9
#define ECAT_P0_RX_CLK P1_1
#define ECAT_P0_RX_ERR P2_6
#define ECAT_P0_TXD3 P1_2
#define ECAT_P0_TXD2 P1_8
#define ECAT_P0_TXD1 P1_7
#define ECAT_P0_TXD0 P1_6
#define ECAT_P0_TX_EN P1_3
#define ECAT_P0_TX_CLK P1_0
/* EtherCAT slave physical layer pin configurations */
#define ECAT_CLK25 P6_0
#define ECAT_PHY_RESET P0_0
#define ECAT_LED_RUN P0_8
#define ECAT_LED_ERR P0_7
#define ECAT_P1_LINK_STATUS P15_3
#define ECAT_P1_LED_LINK_ACT P0_11
#define ECAT_P1_RXD3 P14_14
#define ECAT_P1_RXD2 P14_13
#define ECAT_P1_RXD1 P14_12
#define ECAT_P1_RXD0 P14_7
#define ECAT_P1_RX_DV P14_15
#define ECAT_P1_RX_CLK P14_6
#define ECAT_P1_RX_ERR P15_2
#define ECAT_P1_TXD3 P0_3
#define ECAT_P1_TXD2 P0_2
#define ECAT_P1_TXD1 P3_2
#define ECAT_P1_TXD0 P3_1
#define ECAT_P1_TX_EN P3_0
#define ECAT_P1_TX_CLK P0_10
/* EtherCAT slave physical layer Port 0 pin configurations */
#define ECAT_P0_LINK_STATUS P1_15
#define ECAT_P0_LED_LINK_ACT P6_3
#define ECAT_P0_RXD3 P5_7
#define ECAT_P0_RXD2 P5_2
#define ECAT_P0_RXD1 P5_1
#define ECAT_P0_RXD0 P5_0
#define ECAT_P0_RX_DV P5_6
#define ECAT_P0_RX_CLK P5_4
#define ECAT_P0_RX_ERR P2_6
#define ECAT_P0_TXD3 P6_6
#define ECAT_P0_TXD2 P6_5
#define ECAT_P0_TXD1 P6_4
#define ECAT_P0_TXD0 P6_2
#define ECAT_P0_TX_EN P6_1
#define ECAT_P0_TX_CLK P5_5
/* EtherCAT slave physical layer Port 1 pin configurations */
#define ECAT_P1_LINK_STATUS P3_4
#define ECAT_P1_LED_LINK_ACT P3_12
#define ECAT_P1_RXD3 P0_4
#define ECAT_P1_RXD2 P0_5
#define ECAT_P1_RXD1 P0_6
#define ECAT_P1_RXD0 P0_11
#define ECAT_P1_RX_DV P0_9
#define ECAT_P1_RX_CLK P0_1
#define ECAT_P1_RX_ERR P15_2
#define ECAT_P1_TXD3 P0_3
#define ECAT_P1_TXD2 P0_2
#define ECAT_P1_TXD1 P3_2
#define ECAT_P1_TXD0 P3_1
#define ECAT_P1_TX_EN P3_0
#define ECAT_P1_TX_CLK P0_10
/* configure outputs */
#define AF_ECAT0_P0_TXD3 P6_6_AF_ECAT0_P0_TXD3
#define AF_ECAT0_P0_TXD2 P6_5_AF_ECAT0_P0_TXD2
#define AF_ECAT0_P0_TXD1 P6_4_AF_ECAT0_P0_TXD1
#define AF_ECAT0_P0_TXD0 P6_2_AF_ECAT0_P0_TXD0
#define AF_ECAT0_P0_TX_EN P6_1_AF_ECAT0_P0_TX_ENA
#define AF_ECAT0_P1_TXD3 P0_3_AF_ECAT0_P1_TXD3
#define AF_ECAT0_P1_TXD2 P0_2_AF_ECAT0_P1_TXD2
#define AF_ECAT0_P1_TXD1 P3_2_AF_ECAT0_P1_TXD1
#define AF_ECAT0_P1_TXD0 P3_1_AF_ECAT0_P1_TXD0
#define AF_ECAT0_P1_TX_EN P3_0_AF_ECAT0_P1_TX_ENA
#define AF_ECAT0_CLK25 P6_0_AF_ECAT0_PHY_CLK25
#define AF_ECAT0_MCLK P3_3_AF_ECAT0_MCLK
#define AF_ECAT0_P0_LED_LINK_ACT P6_3_AF_ECAT0_P0_LED_LINK_ACT
#define AF_ECAT0_P1_LED_LINK_ACT P3_12_AF_ECAT0_P1_LED_LINK_ACT
#define AF_ECAT0_LED_RUN P0_8_AF_ECAT0_LED_RUN
#define AF_ECAT0_LED_ERR P0_7_AF_ECAT0_LED_ERR
#define AF_ECAT0_MDO P0_12_HWCTRL_ECAT0_MDO
#define AF_ECAT0_PHY_RESET P0_0_AF_ECAT0_PHY_RESET
#define ECAT_PORT_CTRL_MDIO XMC_ECAT_PORT_CTRL_MDIO_P0_12
#define ECAT_PORT0_CTRL_RXD0 XMC_ECAT_PORT0_CTRL_RXD0_P5_0
#define ECAT_PORT0_CTRL_RXD1 XMC_ECAT_PORT0_CTRL_RXD1_P5_1
#define ECAT_PORT0_CTRL_RXD2 XMC_ECAT_PORT0_CTRL_RXD2_P5_2
#define ECAT_PORT0_CTRL_RXD3 XMC_ECAT_PORT0_CTRL_RXD3_P5_7
#define ECAT_PORT0_CTRL_RX_CLK XMC_ECAT_PORT0_CTRL_RX_CLK_P5_4
#define ECAT_PORT0_CTRL_RX_DV XMC_ECAT_PORT0_CTRL_RX_DV_P5_6
#define ECAT_PORT0_CTRL_RX_ERR XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6
#define ECAT_PORT0_CTRL_LINK XMC_ECAT_PORT0_CTRL_LINK_P1_15
#define ECAT_PORT0_CTRL_TX_CLK XMC_ECAT_PORT0_CTRL_TX_CLK_P5_5
#define ECAT_PORT0_CTRL_TX_SHIFT XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS
#define ECAT_PORT1_CTRL_RXD0 XMC_ECAT_PORT1_CTRL_RXD0_P0_11
#define ECAT_PORT1_CTRL_RXD1 XMC_ECAT_PORT1_CTRL_RXD1_P0_6
#define ECAT_PORT1_CTRL_RXD2 XMC_ECAT_PORT1_CTRL_RXD2_P0_5
#define ECAT_PORT1_CTRL_RXD3 XMC_ECAT_PORT1_CTRL_RXD3_P0_4
#define ECAT_PORT1_CTRL_RX_CLK XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1
#define ECAT_PORT1_CTRL_RX_DV XMC_ECAT_PORT1_CTRL_RX_DV_P0_9
#define ECAT_PORT1_CTRL_RX_ERR XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2
#define ECAT_PORT1_CTRL_LINK XMC_ECAT_PORT1_CTRL_LINK_P3_4
#define ECAT_PORT1_CTRL_TX_CLK XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10
#define ECAT_PORT1_CTRL_TX_SHIFT XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS
#endif
#ifdef XMC4300_F100x256
#define ECAT_MDO P0_12
#define ECAT_MCLK P3_3
#define ECAT_PORT_CTRL_LATCHIN0 XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5
#define ECAT_PORT_CTRL_LATCHIN1 XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4
#define ECAT_PHYADDR_OFFSET 0
#define ECAT_CLK25 P1_13
#define ECAT_PHY_RESET P2_10
#define ECAT_LED_RUN P1_11
#define ECAT_LED_ERR P1_10
#define ECAT_P0_LINK_STATUS P1_15
#define ECAT_P0_LED_LINK_ACT P1_12
#define ECAT_P0_RXD3 P5_7
#define ECAT_P0_RXD2 P5_2
#define ECAT_P0_RXD1 P5_1
#define ECAT_P0_RXD0 P1_4
#define ECAT_P0_RX_DV P1_9
#define ECAT_P0_RX_CLK P1_1
#define ECAT_P0_RX_ERR P2_6
#define ECAT_P0_TXD3 P1_2
#define ECAT_P0_TXD2 P1_8
#define ECAT_P0_TXD1 P1_7
#define ECAT_P0_TXD0 P1_6
#define ECAT_P0_TX_EN P1_3
#define ECAT_P0_TX_CLK P1_0
#define ECAT_P1_LINK_STATUS P15_3
#define ECAT_P1_LED_LINK_ACT P0_11
#define ECAT_P1_RXD3 P14_14
#define ECAT_P1_RXD2 P14_13
#define ECAT_P1_RXD1 P14_12
#define ECAT_P1_RXD0 P14_7
#define ECAT_P1_RX_DV P14_15
#define ECAT_P1_RX_CLK P14_6
#define ECAT_P1_RX_ERR P15_2
#define ECAT_P1_TXD3 P0_3
#define ECAT_P1_TXD2 P0_2
#define ECAT_P1_TXD1 P3_2
#define ECAT_P1_TXD0 P3_1
#define ECAT_P1_TX_EN P3_0
#define ECAT_P1_TX_CLK P0_10
/* configure outputs */
#define AF_ECAT0_P0_TXD3 P1_2_AF_ECAT0_P0_TXD3
#define AF_ECAT0_P0_TXD2 P1_8_AF_ECAT0_P0_TXD2
#define AF_ECAT0_P0_TXD1 P1_7_AF_ECAT0_P0_TXD1
#define AF_ECAT0_P0_TXD0 P1_6_AF_ECAT0_P0_TXD0
#define AF_ECAT0_P0_TX_EN P1_3_AF_ECAT0_P0_TX_ENA
#define AF_ECAT0_P1_TXD3 P0_3_AF_ECAT0_P1_TXD3
#define AF_ECAT0_P1_TXD2 P0_2_AF_ECAT0_P1_TXD2
#define AF_ECAT0_P1_TXD1 P3_2_AF_ECAT0_P1_TXD1
#define AF_ECAT0_P1_TXD0 P3_1_AF_ECAT0_P1_TXD0
#define AF_ECAT0_P1_TX_EN P3_0_AF_ECAT0_P1_TX_ENA
#define AF_ECAT0_CLK25 P1_13_AF_ECAT0_PHY_CLK25
#define AF_ECAT0_MCLK P3_3_AF_ECAT0_MCLK
#define AF_ECAT0_P0_LED_LINK_ACT P1_12_AF_ECAT0_P0_LED_LINK_ACT
#define AF_ECAT0_P1_LED_LINK_ACT P0_11_AF_ECAT0_P1_LED_LINK_ACT
#define AF_ECAT0_LED_RUN P1_11_AF_ECAT0_LED_RUN
#define AF_ECAT0_LED_ERR P1_10_AF_ECAT0_LED_ERR
#define AF_ECAT0_MDO P0_12_HWCTRL_ECAT0_MDO
#define AF_ECAT0_PHY_RESET P2_10_AF_ECAT0_PHY_RESET
#define ECAT_PORT_CTRL_MDIO XMC_ECAT_PORT_CTRL_MDIO_P0_12
#define ECAT_PORT0_CTRL_RXD0 XMC_ECAT_PORT0_CTRL_RXD0_P1_4
#define ECAT_PORT0_CTRL_RXD1 XMC_ECAT_PORT0_CTRL_RXD1_P5_1
#define ECAT_PORT0_CTRL_RXD2 XMC_ECAT_PORT0_CTRL_RXD2_P5_2
#define ECAT_PORT0_CTRL_RXD3 XMC_ECAT_PORT0_CTRL_RXD3_P5_7
#define ECAT_PORT0_CTRL_RX_CLK XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1
#define ECAT_PORT0_CTRL_RX_DV XMC_ECAT_PORT0_CTRL_RX_DV_P1_9
#define ECAT_PORT0_CTRL_RX_ERR XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6
#define ECAT_PORT0_CTRL_LINK XMC_ECAT_PORT0_CTRL_LINK_P1_15
#define ECAT_PORT0_CTRL_TX_CLK XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0
#define ECAT_PORT1_CTRL_RXD0 XMC_ECAT_PORT1_CTRL_RXD0_P14_7
#define ECAT_PORT1_CTRL_RXD1 XMC_ECAT_PORT1_CTRL_RXD1_P14_12
#define ECAT_PORT1_CTRL_RXD2 XMC_ECAT_PORT1_CTRL_RXD2_P14_13
#define ECAT_PORT1_CTRL_RXD3 XMC_ECAT_PORT1_CTRL_RXD3_P14_14
#define ECAT_PORT1_CTRL_RX_CLK XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6
#define ECAT_PORT1_CTRL_RX_DV XMC_ECAT_PORT1_CTRL_RX_DV_P14_15
#define ECAT_PORT1_CTRL_RX_ERR XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2
#define ECAT_PORT1_CTRL_LINK XMC_ECAT_PORT1_CTRL_LINK_P15_3
#define ECAT_PORT1_CTRL_TX_CLK XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10
#endif
#define ESCADDR(x) (((uint8_t *) ECAT0_BASE) + x)
static const XMC_ECAT_PORT_CTRL_t port_control = {
.common = {
.mdio = XMC_ECAT_PORT_CTRL_MDIO_P0_12
.mdio = ECAT_PORT_CTRL_MDIO
},
.port0 = {
.rxd0 = XMC_ECAT_PORT0_CTRL_RXD0_P1_4,
.rxd1 = XMC_ECAT_PORT0_CTRL_RXD1_P5_1,
.rxd2 = XMC_ECAT_PORT0_CTRL_RXD2_P5_2,
.rxd3 = XMC_ECAT_PORT0_CTRL_RXD3_P5_7,
.rx_clk = XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1,
.rx_dv = XMC_ECAT_PORT0_CTRL_RX_DV_P1_9,
.rx_err = XMC_ECAT_PORT0_CTRL_RX_ERR_P2_6,
.link = XMC_ECAT_PORT0_CTRL_LINK_P1_15,
.tx_clk = XMC_ECAT_PORT0_CTRL_TX_CLK_P1_0
.rxd0 = ECAT_PORT0_CTRL_RXD0,
.rxd1 = ECAT_PORT0_CTRL_RXD1,
.rxd2 = ECAT_PORT0_CTRL_RXD2,
.rxd3 = ECAT_PORT0_CTRL_RXD3,
.rx_clk = ECAT_PORT0_CTRL_RX_CLK,
.rx_dv = ECAT_PORT0_CTRL_RX_DV,
.rx_err = ECAT_PORT0_CTRL_RX_ERR,
.link = ECAT_PORT0_CTRL_LINK,
.tx_clk = ECAT_PORT0_CTRL_TX_CLK
},
.port1 = {
.rxd0 = XMC_ECAT_PORT1_CTRL_RXD0_P14_7,
.rxd1 = XMC_ECAT_PORT1_CTRL_RXD1_P14_12,
.rxd2 = XMC_ECAT_PORT1_CTRL_RXD2_P14_13,
.rxd3 = XMC_ECAT_PORT1_CTRL_RXD3_P14_14,
.rx_clk = XMC_ECAT_PORT1_CTRL_RX_CLK_P14_6,
.rx_dv = XMC_ECAT_PORT1_CTRL_RX_DV_P14_15,
.rx_err = XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2,
.link = XMC_ECAT_PORT1_CTRL_LINK_P15_3,
.tx_clk = XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10
.rxd0 = ECAT_PORT1_CTRL_RXD0,
.rxd1 = ECAT_PORT1_CTRL_RXD1,
.rxd2 = ECAT_PORT1_CTRL_RXD2,
.rxd3 = ECAT_PORT1_CTRL_RXD3,
.rx_clk = ECAT_PORT1_CTRL_RX_CLK,
.rx_dv = ECAT_PORT1_CTRL_RX_DV,
.rx_err = ECAT_PORT1_CTRL_RX_ERR,
.link = ECAT_PORT1_CTRL_LINK,
.tx_clk = ECAT_PORT1_CTRL_TX_CLK
}
};
@ -210,26 +357,27 @@ void ESC_init (const void * arg)
XMC_ECAT_Init(&ecat_config);
/* configure outputs */
init_output_sharp(ECAT_P0_TXD3, P1_2_AF_ECAT0_P0_TXD3);
init_output_sharp(ECAT_P0_TXD2, P1_8_AF_ECAT0_P0_TXD2);
init_output_sharp(ECAT_P0_TXD1, P1_7_AF_ECAT0_P0_TXD1);
init_output_sharp(ECAT_P0_TXD0, P1_6_AF_ECAT0_P0_TXD0);
init_output_sharp(ECAT_P0_TX_EN, P1_3_AF_ECAT0_P0_TX_ENA);
init_output_sharp(ECAT_P1_TXD3, P0_3_AF_ECAT0_P1_TXD3);
init_output_sharp(ECAT_P1_TXD2, P0_2_AF_ECAT0_P1_TXD2);
init_output_sharp(ECAT_P1_TXD1, P3_2_AF_ECAT0_P1_TXD1);
init_output_sharp(ECAT_P1_TXD0, P3_1_AF_ECAT0_P1_TXD0);
init_output_sharp(ECAT_P1_TX_EN, P3_0_AF_ECAT0_P1_TX_ENA);
init_output_sharp(ECAT_CLK25, P1_13_AF_ECAT0_PHY_CLK25);
init_output_sharp(ECAT_MCLK, P3_3_AF_ECAT0_MCLK);
init_output_sharp(ECAT_P0_TXD3, AF_ECAT0_P0_TXD3);
init_output_sharp(ECAT_P0_TXD2, AF_ECAT0_P0_TXD2);
init_output_sharp(ECAT_P0_TXD1, AF_ECAT0_P0_TXD1);
init_output_sharp(ECAT_P0_TXD0, AF_ECAT0_P0_TXD0);
init_output_sharp(ECAT_P0_TX_EN, AF_ECAT0_P0_TX_EN);
init_output_sharp(ECAT_P1_TXD3, AF_ECAT0_P1_TXD3);
init_output_sharp(ECAT_P1_TXD2, AF_ECAT0_P1_TXD2);
init_output_sharp(ECAT_P1_TXD1, AF_ECAT0_P1_TXD1);
init_output_sharp(ECAT_P1_TXD0, AF_ECAT0_P1_TXD0);
init_output_sharp(ECAT_P1_TX_EN, AF_ECAT0_P1_TX_EN);
init_output_sharp(ECAT_CLK25, AF_ECAT0_CLK25);
init_output_sharp(ECAT_MCLK, AF_ECAT0_MCLK);
init_output_soft(ECAT_P0_LED_LINK_ACT, P1_12_AF_ECAT0_P0_LED_LINK_ACT);
init_output_soft(ECAT_P1_LED_LINK_ACT, P0_11_AF_ECAT0_P1_LED_LINK_ACT);
init_output_soft(ECAT_LED_RUN, P1_11_AF_ECAT0_LED_RUN);
init_output_soft(ECAT_LED_ERR, P1_10_AF_ECAT0_LED_ERR);
init_output_soft(ECAT_P0_LED_LINK_ACT, AF_ECAT0_P0_LED_LINK_ACT);
init_output_soft(ECAT_P1_LED_LINK_ACT, AF_ECAT0_P1_LED_LINK_ACT);
init_output_soft(ECAT_LED_RUN, AF_ECAT0_LED_RUN);
init_output_soft(ECAT_LED_ERR, AF_ECAT0_LED_ERR);
XMC_GPIO_SetHardwareControl(ECAT_MDO, P0_12_HWCTRL_ECAT0_MDO);
init_input(ECAT_MDO);
XMC_GPIO_SetHardwareControl(ECAT_MDO, AF_ECAT0_MDO);
init_output_soft(ECAT_PHY_RESET, P2_10_AF_ECAT0_PHY_RESET);
init_output_soft(ECAT_PHY_RESET, AF_ECAT0_PHY_RESET);
}

26
soes/hal/xmc4/esc_hw_eep.c
View File

@ -40,7 +40,11 @@
#include <string.h>
#include "sii_eeprom.h"
extern const uint8_t _binary_sii_eeprom_bin_start;
extern const uint8_t _binary_sii_eeprom_bin_end;
#define SII_EE_DEFLT (&_binary_sii_eeprom_bin_start)
#define SII_EE_DEFLT_SIZE (uint32_t)(&_binary_sii_eeprom_bin_end - &_binary_sii_eeprom_bin_start)
#if EEP_BYTES_PER_BLOCK > EEP_BYTES_PER_SECTOR
#error EEP_BYTES_PER_BLOCK needs to fit into EEP_BYTES_PER_SECTOR
@ -85,13 +89,13 @@ static const XMC_GPIO_CONFIG_t gpio_config_btn = {
.output_strength = 0
};
#define EEP_DEFAULT_BTN_INIT() XMC_GPIO_Init(EEP_DEFAULT_BTN, &gpio_config_btn)
#define EEP_DEFAULT_BTN_STATE() XMC_GPIO_GetInput(EEP_DEFAULT_BTN)
#define EEP_DEFAULT_BTN_INIT() XMC_GPIO_Init(EEP_DEFAULT_BTN, &gpio_config_btn)
#define EEP_DEFAULT_BTN_STATE() XMC_GPIO_GetInput(EEP_DEFAULT_BTN)
#else
#define EEP_DEFAULT_BTN_INIT() { }
#define EEP_DEFAULT_BTN_STATE() 0
#define EEP_DEFAULT_BTN_INIT() { }
#define EEP_DEFAULT_BTN_STATE() 0
#endif
@ -103,15 +107,15 @@ static const XMC_GPIO_CONFIG_t gpio_config_led = {
.output_strength = XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE
};
#define EEP_BUSY_LED_INIT() XMC_GPIO_Init(EEP_BUSY_LED, &gpio_config_led)
#define EEP_BUSY_LED_ON() XMC_GPIO_SetOutputHigh(EEP_BUSY_LED)
#define EEP_BUSY_LED_OFF() XMC_GPIO_SetOutputLow(EEP_BUSY_LED)
#define EEP_BUSY_LED_INIT() XMC_GPIO_Init(EEP_BUSY_LED, &gpio_config_led)
#define EEP_BUSY_LED_ON() XMC_GPIO_SetOutputHigh(EEP_BUSY_LED)
#define EEP_BUSY_LED_OFF() XMC_GPIO_SetOutputLow(EEP_BUSY_LED)
#else
#define EEP_BUSY_LED_INIT() { }
#define EEP_BUSY_LED_ON() { }
#define EEP_BUSY_LED_OFF() { }
#define EEP_BUSY_LED_INIT() { }
#define EEP_BUSY_LED_ON() { }
#define EEP_BUSY_LED_OFF() { }
#endif

41
soes/hal/xmc4/esc_hw_eep.h
View File

@ -45,25 +45,40 @@
#include "xmc_fce.h"
/* if defined: reload default EEPROM content if pulled low */
#define EEP_DEFAULT_BTN P3_4
#ifdef XMC4800_F144x2048
#define EEP_DEFAULT_BTN P15_13
/* if defined: flash BUSY indicator */
#define EEP_BUSY_LED P4_0
#define EEP_BUSY_LED P5_9
#endif
#ifdef XMC4300_F100x256
#define EEP_DEFAULT_BTN P3_4
/* if defined: flash BUSY indicator */
#define EEP_BUSY_LED P4_0
#endif
/* used CRC32 kernel for checksum calculation */
#define EPP_FCE_CRC32 XMC_FCE_CRC32_0
#define EPP_FCE_CRC32 XMC_FCE_CRC32_0
/* idle timeout in ns before actual flash write will be issued */
#define EEP_IDLE_TIMEOUT 100000000
#define EEP_IDLE_TIMEOUT 100000000
/* Packes per emulated EEPROM block*/
#define EEP_PAGES_PER_BLOCK 16
#define EEP_PAGES_PER_BLOCK 16
/* flash sector select */
#define EEP_BYTES_PER_SECTOR 0x04000
#define EEP_SECTOR_A XMC_FLASH_SECTOR_6
#define EEP_SECTOR_B XMC_FLASH_SECTOR_7
#ifdef XMC4800_F144x2048
#define EEP_BYTES_PER_SECTOR 0x040000
#define EEP_SECTOR_A XMC_FLASH_SECTOR_14
#define EEP_SECTOR_B XMC_FLASH_SECTOR_15
#endif
#ifdef XMC4300_F100x256
#define EEP_BYTES_PER_SECTOR 0x04000
#define EEP_SECTOR_A XMC_FLASH_SECTOR_6
#define EEP_SECTOR_B XMC_FLASH_SECTOR_7
#endif
/* block header */
typedef struct CC_PACKED
{
@ -72,12 +87,12 @@ typedef struct CC_PACKED
} eep_header_t;
/* calulate resulting sizes */
#define EEP_BYTES_PER_BLOCK (EEP_PAGES_PER_BLOCK * XMC_FLASH_BYTES_PER_PAGE)
#define EPP_BLOCKS_PER_SECT (EEP_BYTES_PER_SECTOR / EEP_BYTES_PER_BLOCK)
#define EEP_DATA_BYTES (EEP_BYTES_PER_BLOCK - sizeof(eep_header_t))
#define EEP_BYTES_PER_BLOCK (EEP_PAGES_PER_BLOCK * XMC_FLASH_BYTES_PER_PAGE)
#define EPP_BLOCKS_PER_SECT (EEP_BYTES_PER_SECTOR / EEP_BYTES_PER_BLOCK)
#define EEP_DATA_BYTES (EEP_BYTES_PER_BLOCK - sizeof(eep_header_t))
/* eeprom size increments in steps of 0x80 bytes */
#define EEP_EMU_BYTES (EEP_DATA_BYTES & ~0x7f)
#define EEP_EMU_BYTES (EEP_DATA_BYTES & ~0x7f)
/* block structure */
typedef struct CC_PACKED