176 lines
14 KiB
C
176 lines
14 KiB
C
/*
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* Licensed under the GNU General Public License version 2 with exceptions. See
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* LICENSE file in the project root for full license information
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*/
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/** \file
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* \brief
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* ESC hardware specifoc EEPROM emulation functions.
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*/
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#ifndef __esc_hw__
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#define __esc_hw__
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#include <kern/kern.h>
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/* ================================================================================ */
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/* ================ ECAT [ECAT0] ================ */
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/* ================================================================================ */
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/**
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* @brief EtherCAT 0 (ECAT)
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*/
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typedef struct esc_registers
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{ /*!< (@ 0x54010000) ECAT Structure */
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uint8_t TYPE; /*!< (@ 0x54010000) Type of EtherCAT Controller */
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uint8_t REVISION; /*!< (@ 0x54010001) Revision of EtherCAT Controller */
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uint16_t BUILD; /*!< (@ 0x54010002) Build Version */
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uint8_t FMMU_NUM; /*!< (@ 0x54010004) FMMUs Supported */
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uint8_t SYNC_MANAGER; /*!< (@ 0x54010005) SyncManagers Supported */
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uint8_t RAM_SIZE; /*!< (@ 0x54010006) RAM Size */
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uint8_t PORT_DESC; /*!< (@ 0x54010007) Port Descriptor */
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uint16_t FEATURE; /*!< (@ 0x54010008) ESC Features Supported */
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uint16_t RESERVED[3];
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uint16_t STATION_ADR; /*!< (@ 0x54010010) Configured Station Address */
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uint16_t STATION_ALIAS; /*!< (@ 0x54010012) Configured Station Alias */
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uint32_t RESERVED1[3];
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uint8_t WR_REG_ENABLE; /*!< (@ 0x54010020) Write Register Enable */
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uint8_t WR_REG_PROTECT; /*!< (@ 0x54010021) Write Register Protection */
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uint16_t RESERVED2[7];
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uint8_t ESC_WR_ENABLE; /*!< (@ 0x54010030) ESC Write Enable */
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uint8_t ESC_WR_PROTECT; /*!< (@ 0x54010031) ESC Write Protection */
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uint16_t RESERVED3[7];
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union
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{
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uint8_t ESC_RESET_ECAT_READMode; /*!< (@ 0x54010040) ESC Reset ECAT [READ Mode] */
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uint8_t ESC_RESET_ECAT_WRITEMode; /*!< (@ 0x54010040) ESC Reset ECAT [WRITE Mode] */
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};
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union {
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uint8_t ESC_RESET_PDI_READMode; /*!< (@ 0x54010041) ESC Reset PDI [READ Mode] */
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uint8_t ESC_RESET_PDI_WRITEMode; /*!< (@ 0x54010041) ESC Reset PDI [WRITE Mode] */
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};
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uint16_t RESERVED4[95];
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uint32_t ESC_DL_CONTROL; /*!< (@ 0x54010100) ESC DL Control */
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uint32_t RESERVED5;
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uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x54010108) Physical Read/Write Offset */
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uint16_t RESERVED6[3];
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uint16_t ESC_DL_STATUS; /*!< (@ 0x54010110) ESC DL Status */
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uint16_t RESERVED7[7];
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uint16_t AL_CONTROL; /*!< (@ 0x54010120) AL Control */
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uint16_t RESERVED8[7];
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uint16_t AL_STATUS; /*!< (@ 0x54010130) AL Status */
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uint16_t RESERVED9;
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uint16_t AL_STATUS_CODE; /*!< (@ 0x54010134) AL Status Code */
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uint16_t RESERVED10;
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uint8_t RUN_LED; /*!< (@ 0x54010138) RUN LED Override */
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uint8_t ERR_LED; /*!< (@ 0x54010139) RUN ERR Override */
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uint16_t RESERVED11[3];
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uint8_t PDI_CONTROL; /*!< (@ 0x54010140) PDI Control */
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uint8_t ESC_CONFIG; /*!< (@ 0x54010141) ESC Configuration */
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uint16_t RESERVED12[7];
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uint8_t PDI_CONFIG; /*!< (@ 0x54010150) PDI Control */
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uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x54010151) Sync/Latch[1:0] PDI Configuration */
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uint16_t PDI_EXT_CONFIG; /*!< (@ 0x54010152) PDI Synchronous Microcontroller extended Configuration */
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uint32_t RESERVED13[43];
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uint16_t EVENT_MASK; /*!< (@ 0x54010200) ECAT Event Mask */
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uint16_t RESERVED14;
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uint32_t AL_EVENT_MASK; /*!< (@ 0x54010204) PDI AL Event Mask */
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uint32_t RESERVED15[2];
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uint16_t EVENT_REQ; /*!< (@ 0x54010210) ECAT Event Request */
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uint16_t RESERVED16[7];
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uint32_t AL_EVENT_REQ; /*!< (@ 0x54010220) AL Event Request */
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uint32_t RESERVED17[55];
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uint16_t RX_ERR_COUNT0; /*!< (@ 0x54010300) RX Error Counter Port 0 */
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uint16_t RX_ERR_COUNT1; /*!< (@ 0x54010302) RX Error Counter Port 1 */
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uint32_t RESERVED18;
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uint8_t FWD_RX_ERR_COUNT0; /*!< (@ 0x54010308) Forwarded RX Error Counter Port 0 */
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uint8_t FWD_RX_ERR_COUNT1; /*!< (@ 0x54010309) Forwarded RX Error Counter Port 1 */
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uint16_t RESERVED19;
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uint8_t PROC_ERR_COUNT; /*!< (@ 0x5401030C) ECAT Processing Unit Error Counter */
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uint8_t PDI_ERR_COUNT; /*!< (@ 0x5401030D) PDI Error Counter */
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uint16_t RESERVED20;
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uint8_t LOST_LINK_COUNT0; /*!< (@ 0x54010310) Lost Link Counter Port 0 */
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uint8_t LOST_LINK_COUNT1; /*!< (@ 0x54010311) Lost Link Counter Port 1 */
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uint16_t RESERVED21[119];
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uint16_t WD_DIVIDE; /*!< (@ 0x54010400) Watchdog Divider */
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uint16_t RESERVED22[7];
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uint16_t WD_TIME_PDI; /*!< (@ 0x54010410) Watchdog Time PDI */
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uint16_t RESERVED23[7];
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uint16_t WD_TIME_PDATA; /*!< (@ 0x54010420) Watchdog Time Process Data */
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uint16_t RESERVED24[15];
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uint16_t WD_STAT_PDATA; /*!< (@ 0x54010440) Watchdog Status Process Data */
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uint8_t WD_COUNT_PDATA; /*!< (@ 0x54010442) Watchdog Counter Process Data */
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uint8_t WD_COUNT_PDI; /*!< (@ 0x54010443) Watchdog Counter PDI */
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uint32_t RESERVED25[47];
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uint8_t EEP_CONF; /*!< (@ 0x54010500) EEPROM Configuration */
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uint8_t EEP_STATE; /*!< (@ 0x54010501) EEPROM PDI Access State */
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uint16_t EEP_CONT_STAT; /*!< (@ 0x54010502) EEPROM Control/Status */
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uint32_t EEP_ADR; /*!< (@ 0x54010504) EEPROM Address */
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uint32_t EEP_DATA[2]; /*!< (@ 0x54010508) EEPROM Read/Write data */
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uint16_t MII_CONT_STAT; /*!< (@ 0x54010510) MII Management Control/Status */
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uint8_t MII_PHY_ADR; /*!< (@ 0x54010512) PHY Address */
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uint8_t MII_PHY_REG_ADR; /*!< (@ 0x54010513) PHY Register Address */
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uint16_t MII_PHY_DATA; /*!< (@ 0x54010514) PHY Data */
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uint8_t MII_ECAT_ACS_STATE; /*!< (@ 0x54010516) MII ECAT ACS STATE */
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uint8_t MII_PDI_ACS_STATE; /*!< (@ 0x54010517) MII PDI ACS STATE */
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uint32_t RESERVED26[250];
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uint32_t DC_RCV_TIME_PORT0; /*!< (@ 0x54010900) Receive Time Port 0 */
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uint32_t DC_RCV_TIME_PORT1; /*!< (@ 0x54010904) Receive Time Port 1 */
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uint32_t RESERVED27[2];
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union
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{
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uint32_t READMode_DC_SYS_TIME[2]; /*!< (@ 0x54010910) System Time read access */
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uint32_t DC_SYS_TIME_WRITEMode; /*!< (@ 0x54010910) System Time [WRITE Mode] */
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};
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uint32_t RECEIVE_TIME_PU[2]; /*!< (@ 0x54010918) Local time of the beginning of a frame */
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uint32_t DC_SYS_TIME_OFFSET[2]; /*!< (@ 0x54010920) Difference between local time and System Time */
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uint32_t DC_SYS_TIME_DELAY; /*!< (@ 0x54010928) System Time Delay */
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uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x5401092C) System Time Difference */
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uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x54010930) Speed Counter Start */
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uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x54010932) Speed Counter Diff */
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uint8_t DC_SYS_TIME_FIL_DEPTH; /*!< (@ 0x54010934) System Time Difference Filter Depth */
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uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x54010935) Speed Counter Filter Depth */
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uint16_t RESERVED28[37];
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uint8_t DC_CYC_CONT; /*!< (@ 0x54010980) Cyclic Unit Control */
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uint8_t DC_ACT; /*!< (@ 0x54010981) Activation register */
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uint16_t DC_PULSE_LEN; /*!< (@ 0x54010982) Pulse Length of SyncSignals */
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uint8_t DC_ACT_STAT; /*!< (@ 0x54010984) Activation Status */
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uint8_t RESERVED29[9];
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uint8_t DC_SYNC0_STAT; /*!< (@ 0x5401098E) SYNC0 Status */
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uint8_t DC_SYNC1_STAT; /*!< (@ 0x5401098F) SYNC1 Status */
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uint32_t DC_CYC_START_TIME[2]; /*!< (@ 0x54010990) Start Time Cyclic Operation */
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uint32_t DC_NEXT_SYNC1_PULSE[2]; /*!< (@ 0x54010998) System time of next SYNC1 pulse in ns */
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uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x540109A0) SYNC0 Cycle Time */
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uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x540109A4) SYNC1 Cycle Time */
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uint8_t DC_LATCH0_CONT; /*!< (@ 0x540109A8) Latch0 Control */
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uint8_t DC_LATCH1_CONT; /*!< (@ 0x540109A9) Latch1 Control */
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uint32_t RESERVED30;
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uint8_t DC_LATCH0_STAT; /*!< (@ 0x540109AE) Latch0 Status */
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uint8_t DC_LATCH1_STAT; /*!< (@ 0x540109AF) Latch1 Status */
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uint32_t DC_LATCH0_TIME_POS[2]; /*!< (@ 0x540109B0) Register captures System time at the positive
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edge of the Latch0 signal */
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uint32_t DC_LATCH0_TIME_NEG[2]; /*!< (@ 0x540109B8) Register captures System time at the negative
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edge of the Latch0 signal */
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uint32_t DC_LATCH1_TIME_POS[2]; /*!< (@ 0x540109C0) Register captures System time at the positive
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edge of the Latch1 signal */
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uint32_t DC_LATCH1_TIME_NEG[2]; /*!< (@ 0x540109C8) Register captures System time at the negative
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edge of the Latch1 signal */
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uint32_t RESERVED31[8];
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uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x540109F0) EtherCAT Buffer Change Event Time */
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uint32_t RESERVED32;
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uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x540109F8) PDI Buffer Start Event Time */
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uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x540109FC) PDI Buffer Change Event Time */
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uint32_t RESERVED33[256];
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uint32_t ID; /*!< (@ 0x54010E00) ECAT0 Module ID */
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uint32_t RESERVED34;
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uint32_t STATUS; /*!< (@ 0x54010E08) ECAT0 Status */
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} esc_registers_t;
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void EEP_hw_process (void);
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void ESC_eep_handler(void);
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void ESC_interrupt_enable (uint32_t mask);
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void ESC_interrupt_disable (uint32_t mask);
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#endif
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