2018-03-02 13:31:14 +01:00
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/*
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* QEMU RISC-V Board Compatible with SiFive Freedom E SDK
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Provides a board compatible with the SiFive Freedom E SDK:
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*
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* 0) UART
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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* 3) PRCI (Power, Reset, Clock, Interrupt)
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* 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM
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* 5) Flash memory emulated as RAM
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*
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* The Mask ROM reset vector jumps to the flash payload at 0x2040_0000.
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* The OTP ROM and Flash boot code will be emulated in a future version.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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2019-09-06 18:20:01 +02:00
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#include "hw/misc/unimp.h"
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2018-03-02 13:31:14 +01:00
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_e.h"
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2019-09-06 18:19:58 +02:00
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#include "hw/riscv/sifive_e_prci.h"
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2019-06-25 00:11:49 +02:00
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#include "hw/riscv/boot.h"
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2018-03-02 13:31:14 +01:00
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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2019-08-12 07:23:57 +02:00
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#include "sysemu/sysemu.h"
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2018-03-02 13:31:14 +01:00
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#include "exec/address-spaces.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_e_memmap[] = {
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[SIFIVE_E_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
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[SIFIVE_E_OTP] = { 0x20000, 0x2000 },
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[SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_E_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_E_AON] = { 0x10000000, 0x8000 },
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[SIFIVE_E_PRCI] = { 0x10008000, 0x8000 },
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[SIFIVE_E_OTP_CTRL] = { 0x10010000, 0x1000 },
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[SIFIVE_E_GPIO0] = { 0x10012000, 0x1000 },
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[SIFIVE_E_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_E_QSPI0] = { 0x10014000, 0x1000 },
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[SIFIVE_E_PWM0] = { 0x10015000, 0x1000 },
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[SIFIVE_E_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_E_QSPI1] = { 0x10024000, 0x1000 },
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[SIFIVE_E_PWM1] = { 0x10025000, 0x1000 },
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[SIFIVE_E_QSPI2] = { 0x10034000, 0x1000 },
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[SIFIVE_E_PWM2] = { 0x10035000, 0x1000 },
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[SIFIVE_E_XIP] = { 0x20000000, 0x20000000 },
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[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
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};
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static void riscv_sifive_e_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = sifive_e_memmap;
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2020-05-13 19:37:08 +02:00
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SiFiveEState *s = RISCV_E_MACHINE(machine);
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2018-03-02 13:31:14 +01:00
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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2018-03-03 23:52:13 +01:00
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int i;
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2018-03-02 13:31:14 +01:00
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2018-05-04 01:54:02 +02:00
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/* Initialize SoC */
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qom: Less verbose object_initialize_child()
All users of object_initialize_child() pass the obvious child size
argument. Almost all pass &error_abort and no properties. Tiresome.
Rename object_initialize_child() to
object_initialize_child_with_props() to free the name. New
convenience wrapper object_initialize_child() automates the size
argument, and passes &error_abort and no properties.
Rename object_initialize_childv() to
object_initialize_child_with_propsv() for consistency.
Convert callers with this Coccinelle script:
@@
expression parent, propname, type;
expression child, size;
symbol error_abort;
@@
- object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, size, type, &error_abort, NULL)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
symbol error_abort;
@@
- object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL)
+ object_initialize_child(parent, propname, &child, type)
@@
expression parent, propname, type;
expression child, size, err;
expression list props;
@@
- object_initialize_child(parent, propname, child, size, type, err, props)
+ object_initialize_child_with_props(parent, propname, child, size, type, err, props)
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
[Rebased: machine opentitan is new (commit fe0fe4735e7)]
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 07:32:25 +02:00
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object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
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qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 07:32:45 +02:00
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qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
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2018-03-02 13:31:14 +01:00
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/* Data Tightly Integrated Memory */
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
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memmap[SIFIVE_E_DTIM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_DTIM].base, main_mem);
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2018-05-04 01:54:02 +02:00
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/* Mask ROM reset vector */
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2020-05-13 19:42:46 +02:00
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uint32_t reset_vec[2];
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if (s->revb) {
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reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
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} else {
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reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
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}
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reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
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2018-05-04 01:54:02 +02:00
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_E_MROM].base, &address_space_memory);
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if (machine->kernel_filename) {
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2019-11-19 07:21:09 +01:00
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riscv_load_kernel(machine->kernel_filename, NULL);
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2018-05-04 01:54:02 +02:00
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}
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}
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2020-05-13 19:42:46 +02:00
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static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
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{
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SiFiveEState *s = RISCV_E_MACHINE(obj);
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return s->revb;
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}
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static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
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{
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SiFiveEState *s = RISCV_E_MACHINE(obj);
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s->revb = value;
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}
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2020-05-13 19:37:08 +02:00
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static void sifive_e_machine_instance_init(Object *obj)
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{
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2020-05-13 19:42:46 +02:00
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SiFiveEState *s = RISCV_E_MACHINE(obj);
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s->revb = false;
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object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
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sifive_e_machine_set_revb);
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object_property_set_description(obj, "revb",
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"Set on to tell QEMU that it should model "
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"the revB HiFive1 board");
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2020-05-13 19:37:08 +02:00
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}
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static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive E SDK";
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mc->init = riscv_sifive_e_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = SIFIVE_E_CPU;
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}
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static const TypeInfo sifive_e_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_e"),
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.parent = TYPE_MACHINE,
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.class_init = sifive_e_machine_class_init,
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.instance_init = sifive_e_machine_instance_init,
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.instance_size = sizeof(SiFiveEState),
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};
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static void sifive_e_machine_init_register_types(void)
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{
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type_register_static(&sifive_e_machine_typeinfo);
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}
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type_init(sifive_e_machine_init_register_types)
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2018-05-04 01:54:02 +02:00
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static void riscv_sifive_e_soc_init(Object *obj)
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{
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2019-05-18 22:54:23 +02:00
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MachineState *ms = MACHINE(qdev_get_machine());
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2018-05-04 01:54:02 +02:00
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SiFiveESoCState *s = RISCV_E_SOC(obj);
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sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
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object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
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2019-05-18 22:54:23 +02:00
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object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
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2018-05-04 01:54:02 +02:00
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&error_abort);
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sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
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object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
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TYPE_SIFIVE_GPIO);
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2018-05-04 01:54:02 +02:00
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}
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static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
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{
|
2019-05-18 22:54:23 +02:00
|
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
2018-05-04 01:54:02 +02:00
|
|
|
const struct MemmapEntry *memmap = sifive_e_memmap;
|
2019-02-12 18:38:39 +01:00
|
|
|
Error *err = NULL;
|
2018-05-04 01:54:02 +02:00
|
|
|
|
|
|
|
SiFiveESoCState *s = RISCV_E_SOC(dev);
|
|
|
|
MemoryRegion *sys_mem = get_system_memory();
|
|
|
|
|
2020-03-13 20:34:28 +01:00
|
|
|
object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
|
|
|
|
&error_abort);
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
|
2018-05-04 01:54:02 +02:00
|
|
|
|
2018-03-02 13:31:14 +01:00
|
|
|
/* Mask ROM */
|
2020-02-22 18:12:57 +01:00
|
|
|
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
|
|
|
|
memmap[SIFIVE_E_MROM].size, &error_fatal);
|
2018-03-02 13:31:14 +01:00
|
|
|
memory_region_add_subregion(sys_mem,
|
2019-06-14 13:58:41 +02:00
|
|
|
memmap[SIFIVE_E_MROM].base, &s->mask_rom);
|
2018-03-02 13:31:14 +01:00
|
|
|
|
|
|
|
/* MMIO */
|
|
|
|
s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
|
|
|
|
(char *)SIFIVE_E_PLIC_HART_CONFIG,
|
|
|
|
SIFIVE_E_PLIC_NUM_SOURCES,
|
|
|
|
SIFIVE_E_PLIC_NUM_PRIORITIES,
|
|
|
|
SIFIVE_E_PLIC_PRIORITY_BASE,
|
|
|
|
SIFIVE_E_PLIC_PENDING_BASE,
|
|
|
|
SIFIVE_E_PLIC_ENABLE_BASE,
|
|
|
|
SIFIVE_E_PLIC_ENABLE_STRIDE,
|
|
|
|
SIFIVE_E_PLIC_CONTEXT_BASE,
|
|
|
|
SIFIVE_E_PLIC_CONTEXT_STRIDE,
|
|
|
|
memmap[SIFIVE_E_PLIC].size);
|
|
|
|
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
|
2019-05-18 22:54:23 +02:00
|
|
|
memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
|
2020-02-02 14:42:17 +01:00
|
|
|
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.aon",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
|
2019-09-06 18:19:58 +02:00
|
|
|
sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
|
2019-02-12 18:38:39 +01:00
|
|
|
|
|
|
|
/* GPIO */
|
|
|
|
|
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2
This is the same transformation as in the previous commit, except
sysbus_init_child_obj() and realize are too separated for the commit's
Coccinelle script to handle, typically because sysbus_init_child_obj()
is in a device's instance_init() method, and the matching realize is
in its realize() method.
Perhaps a Coccinelle wizard could make it transform that pattern, but
I'm just a bungler, and the best I can do is transforming the two
separate parts separately:
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(OBJECT(child), true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression errp;
expression child;
symbol true;
@@
- object_property_set_bool(child, true, "realized", errp);
+ sysbus_realize(SYS_BUS_DEVICE(child), errp);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
@@
- qdev_init_nofail(DEVICE(child));
+ sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
expression dev;
@@
dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression child;
identifier dev;
@@
DeviceState *dev = DEVICE(child);
...
- qdev_init_nofail(dev);
+ sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal);
// only correct with a matching sysbus_init_child_obj() transformation!
@@
expression parent, name, size, type;
expression child;
symbol true;
@@
- sysbus_init_child_obj(parent, name, child, size, type);
+ sysbus_init_child_XXX(parent, name, child, size, type);
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type)
+ object_initialize_child(parent, propname, child, type)
@@
expression parent, propname, type;
expression child;
@@
- sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type)
+ object_initialize_child(parent, propname, &child, type)
This script is *unsound*: we need to manually verify init and realize
conversions are properly paired.
This commit has only the pairs where object_initialize_child()'s
@child and sysbus_realize()'s @dev argument text match exactly within
the same source file.
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
|
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
|
2019-02-12 18:38:39 +01:00
|
|
|
if (err) {
|
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Map GPIO registers */
|
|
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
|
|
|
|
|
|
|
|
/* Pass all GPIOs to the SOC layer so they are available to the board */
|
|
|
|
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
|
|
|
|
|
|
|
|
/* Connect GPIO interrupts to the PLIC */
|
|
|
|
for (int i = 0; i < 32; i++) {
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
|
|
|
|
qdev_get_gpio_in(DEVICE(s->plic),
|
|
|
|
SIFIVE_E_GPIO0_IRQ0 + i));
|
|
|
|
}
|
|
|
|
|
2018-03-02 13:31:14 +01:00
|
|
|
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
|
2018-04-26 22:54:12 +02:00
|
|
|
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.qspi0",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.pwm0",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
|
2018-12-14 01:19:03 +01:00
|
|
|
sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
|
|
|
|
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.qspi1",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.pwm1",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.qspi2",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
|
2019-09-06 18:20:01 +02:00
|
|
|
create_unimplemented_device("riscv.sifive.e.pwm2",
|
2018-03-02 13:31:14 +01:00
|
|
|
memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
|
|
|
|
|
|
|
|
/* Flash memory */
|
2020-02-22 18:12:57 +01:00
|
|
|
memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
|
2020-02-24 19:51:24 +01:00
|
|
|
memmap[SIFIVE_E_XIP].size, &error_fatal);
|
2019-06-14 13:58:41 +02:00
|
|
|
memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
|
|
|
|
&s->xip_mem);
|
2018-03-02 13:31:14 +01:00
|
|
|
}
|
|
|
|
|
2018-05-04 01:54:02 +02:00
|
|
|
static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = riscv_sifive_e_soc_realize;
|
|
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
|
|
dc->user_creatable = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo riscv_sifive_e_soc_type_info = {
|
|
|
|
.name = TYPE_RISCV_E_SOC,
|
|
|
|
.parent = TYPE_DEVICE,
|
|
|
|
.instance_size = sizeof(SiFiveESoCState),
|
|
|
|
.instance_init = riscv_sifive_e_soc_init,
|
|
|
|
.class_init = riscv_sifive_e_soc_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void riscv_sifive_e_soc_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&riscv_sifive_e_soc_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(riscv_sifive_e_soc_register_types)
|