2005-01-15 13:02:56 +01:00
|
|
|
/*
|
|
|
|
* QEMU Parallel PORT emulation
|
2007-09-16 23:08:06 +02:00
|
|
|
*
|
2005-11-11 00:58:52 +01:00
|
|
|
* Copyright (c) 2003-2005 Fabrice Bellard
|
2007-02-18 00:44:43 +01:00
|
|
|
* Copyright (c) 2007 Marko Kohtala
|
2007-09-16 23:08:06 +02:00
|
|
|
*
|
2005-01-15 13:02:56 +01:00
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
2007-11-17 18:14:51 +01:00
|
|
|
#include "hw.h"
|
|
|
|
#include "qemu-char.h"
|
|
|
|
#include "isa.h"
|
|
|
|
#include "pc.h"
|
2010-06-02 18:48:27 +02:00
|
|
|
#include "sysemu.h"
|
2005-01-15 13:02:56 +01:00
|
|
|
|
|
|
|
//#define DEBUG_PARALLEL
|
|
|
|
|
2007-02-18 00:44:43 +01:00
|
|
|
#ifdef DEBUG_PARALLEL
|
2009-05-13 19:53:17 +02:00
|
|
|
#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
|
2007-02-18 00:44:43 +01:00
|
|
|
#else
|
2009-05-13 19:53:17 +02:00
|
|
|
#define pdebug(fmt, ...) ((void)0)
|
2007-02-18 00:44:43 +01:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#define PARA_REG_DATA 0
|
|
|
|
#define PARA_REG_STS 1
|
|
|
|
#define PARA_REG_CTR 2
|
|
|
|
#define PARA_REG_EPP_ADDR 3
|
|
|
|
#define PARA_REG_EPP_DATA 4
|
|
|
|
|
2005-01-15 13:02:56 +01:00
|
|
|
/*
|
|
|
|
* These are the definitions for the Printer Status Register
|
|
|
|
*/
|
|
|
|
#define PARA_STS_BUSY 0x80 /* Busy complement */
|
|
|
|
#define PARA_STS_ACK 0x40 /* Acknowledge */
|
|
|
|
#define PARA_STS_PAPER 0x20 /* Out of paper */
|
|
|
|
#define PARA_STS_ONLINE 0x10 /* Online */
|
|
|
|
#define PARA_STS_ERROR 0x08 /* Error complement */
|
2007-02-18 00:44:43 +01:00
|
|
|
#define PARA_STS_TMOUT 0x01 /* EPP timeout */
|
2005-01-15 13:02:56 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* These are the definitions for the Printer Control Register
|
|
|
|
*/
|
2007-02-18 00:44:43 +01:00
|
|
|
#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
|
2005-01-15 13:02:56 +01:00
|
|
|
#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
|
|
|
|
#define PARA_CTR_SELECT 0x08 /* Select In complement */
|
|
|
|
#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
|
|
|
|
#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
|
|
|
|
#define PARA_CTR_STROBE 0x01 /* Strobe complement */
|
|
|
|
|
2007-02-18 00:44:43 +01:00
|
|
|
#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
|
|
|
|
|
2011-02-05 15:51:57 +01:00
|
|
|
typedef struct ParallelState {
|
2007-02-18 00:44:43 +01:00
|
|
|
uint8_t dataw;
|
|
|
|
uint8_t datar;
|
|
|
|
uint8_t status;
|
2005-01-15 13:02:56 +01:00
|
|
|
uint8_t control;
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq irq;
|
2005-01-15 13:02:56 +01:00
|
|
|
int irq_pending;
|
|
|
|
CharDriverState *chr;
|
2005-11-11 00:58:52 +01:00
|
|
|
int hw_driver;
|
2007-02-18 00:44:43 +01:00
|
|
|
int epp_timeout;
|
|
|
|
uint32_t last_read_offset; /* For debugging */
|
2007-06-18 20:55:46 +02:00
|
|
|
/* Memory-mapped interface */
|
|
|
|
int it_shift;
|
2011-02-05 15:51:57 +01:00
|
|
|
} ParallelState;
|
2005-01-15 13:02:56 +01:00
|
|
|
|
2009-09-22 13:53:22 +02:00
|
|
|
typedef struct ISAParallelState {
|
|
|
|
ISADevice dev;
|
2009-10-13 13:38:39 +02:00
|
|
|
uint32_t index;
|
2009-09-22 13:53:22 +02:00
|
|
|
uint32_t iobase;
|
|
|
|
uint32_t isairq;
|
|
|
|
ParallelState state;
|
|
|
|
} ISAParallelState;
|
|
|
|
|
2005-01-15 13:02:56 +01:00
|
|
|
static void parallel_update_irq(ParallelState *s)
|
|
|
|
{
|
|
|
|
if (s->irq_pending)
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq_raise(s->irq);
|
2005-01-15 13:02:56 +01:00
|
|
|
else
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq_lower(s->irq);
|
2005-01-15 13:02:56 +01:00
|
|
|
}
|
|
|
|
|
2007-02-18 00:44:43 +01:00
|
|
|
static void
|
|
|
|
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
|
2005-01-15 13:02:56 +01:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-02-18 00:44:43 +01:00
|
|
|
pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
|
|
|
|
|
|
|
|
addr &= 7;
|
|
|
|
switch(addr) {
|
|
|
|
case PARA_REG_DATA:
|
2007-06-07 23:07:11 +02:00
|
|
|
s->dataw = val;
|
|
|
|
parallel_update_irq(s);
|
2007-02-18 00:44:43 +01:00
|
|
|
break;
|
|
|
|
case PARA_REG_CTR:
|
2008-02-10 14:34:48 +01:00
|
|
|
val |= 0xc0;
|
2007-06-07 23:07:11 +02:00
|
|
|
if ((val & PARA_CTR_INIT) == 0 ) {
|
|
|
|
s->status = PARA_STS_BUSY;
|
|
|
|
s->status |= PARA_STS_ACK;
|
|
|
|
s->status |= PARA_STS_ONLINE;
|
|
|
|
s->status |= PARA_STS_ERROR;
|
|
|
|
}
|
|
|
|
else if (val & PARA_CTR_SELECT) {
|
|
|
|
if (val & PARA_CTR_STROBE) {
|
|
|
|
s->status &= ~PARA_STS_BUSY;
|
|
|
|
if ((s->control & PARA_CTR_STROBE) == 0)
|
2011-08-15 18:17:28 +02:00
|
|
|
qemu_chr_fe_write(s->chr, &s->dataw, 1);
|
2007-06-07 23:07:11 +02:00
|
|
|
} else {
|
|
|
|
if (s->control & PARA_CTR_INTEN) {
|
|
|
|
s->irq_pending = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
parallel_update_irq(s);
|
|
|
|
s->control = val;
|
2007-02-18 00:44:43 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint8_t parm = val;
|
2008-08-22 10:57:09 +02:00
|
|
|
int dir;
|
2007-02-18 00:44:43 +01:00
|
|
|
|
|
|
|
/* Sometimes programs do several writes for timing purposes on old
|
|
|
|
HW. Take care not to waste time on writes that do nothing. */
|
|
|
|
|
|
|
|
s->last_read_offset = ~0U;
|
|
|
|
|
2005-01-15 13:02:56 +01:00
|
|
|
addr &= 7;
|
|
|
|
switch(addr) {
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_DATA:
|
|
|
|
if (s->dataw == val)
|
2007-06-07 23:07:11 +02:00
|
|
|
return;
|
|
|
|
pdebug("wd%02x\n", val);
|
|
|
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
|
|
|
|
s->dataw = val;
|
2005-01-15 13:02:56 +01:00
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_STS:
|
2007-06-07 23:07:11 +02:00
|
|
|
pdebug("ws%02x\n", val);
|
|
|
|
if (val & PARA_STS_TMOUT)
|
|
|
|
s->epp_timeout = 0;
|
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_CTR:
|
|
|
|
val |= 0xc0;
|
|
|
|
if (s->control == val)
|
2007-06-07 23:07:11 +02:00
|
|
|
return;
|
|
|
|
pdebug("wc%02x\n", val);
|
2008-08-22 10:57:09 +02:00
|
|
|
|
|
|
|
if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
|
|
|
|
if (val & PARA_CTR_DIR) {
|
|
|
|
dir = 1;
|
|
|
|
} else {
|
|
|
|
dir = 0;
|
|
|
|
}
|
|
|
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
|
|
|
|
parm &= ~PARA_CTR_DIR;
|
|
|
|
}
|
|
|
|
|
2007-06-07 23:07:11 +02:00
|
|
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
|
|
|
|
s->control = val;
|
2005-01-15 13:02:56 +01:00
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_EPP_ADDR:
|
2007-06-07 23:07:11 +02:00
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
|
|
|
|
/* Controls not correct for EPP address cycle, so do nothing */
|
|
|
|
pdebug("wa%02x s\n", val);
|
|
|
|
else {
|
|
|
|
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
|
|
|
|
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
|
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("wa%02x t\n", val);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
pdebug("wa%02x\n", val);
|
|
|
|
}
|
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_EPP_DATA:
|
2007-06-07 23:07:11 +02:00
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
|
|
|
|
/* Controls not correct for EPP data cycle, so do nothing */
|
|
|
|
pdebug("we%02x s\n", val);
|
|
|
|
else {
|
|
|
|
struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
|
|
|
|
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
|
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("we%02x t\n", val);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
pdebug("we%02x\n", val);
|
|
|
|
}
|
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint16_t eppdata = cpu_to_le16(val);
|
|
|
|
int err;
|
|
|
|
struct ParallelIOArg ioarg = {
|
2007-06-07 23:07:11 +02:00
|
|
|
.buffer = &eppdata, .count = sizeof(eppdata)
|
2007-02-18 00:44:43 +01:00
|
|
|
};
|
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
|
2007-06-07 23:07:11 +02:00
|
|
|
/* Controls not correct for EPP data cycle, so do nothing */
|
|
|
|
pdebug("we%04x s\n", val);
|
|
|
|
return;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
|
|
|
|
if (err) {
|
2007-06-07 23:07:11 +02:00
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("we%04x t\n", val);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
else
|
2007-06-07 23:07:11 +02:00
|
|
|
pdebug("we%04x\n", val);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
|
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint32_t eppdata = cpu_to_le32(val);
|
|
|
|
int err;
|
|
|
|
struct ParallelIOArg ioarg = {
|
2007-06-07 23:07:11 +02:00
|
|
|
.buffer = &eppdata, .count = sizeof(eppdata)
|
2007-02-18 00:44:43 +01:00
|
|
|
};
|
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
|
2007-06-07 23:07:11 +02:00
|
|
|
/* Controls not correct for EPP data cycle, so do nothing */
|
|
|
|
pdebug("we%08x s\n", val);
|
|
|
|
return;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
|
|
|
|
if (err) {
|
2007-06-07 23:07:11 +02:00
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("we%08x t\n", val);
|
2005-01-15 13:02:56 +01:00
|
|
|
}
|
2007-02-18 00:44:43 +01:00
|
|
|
else
|
2007-06-07 23:07:11 +02:00
|
|
|
pdebug("we%08x\n", val);
|
2005-01-15 13:02:56 +01:00
|
|
|
}
|
|
|
|
|
2007-02-18 00:44:43 +01:00
|
|
|
static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
|
2005-01-15 13:02:56 +01:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint32_t ret = 0xff;
|
|
|
|
|
|
|
|
addr &= 7;
|
|
|
|
switch(addr) {
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_DATA:
|
2007-06-07 23:07:11 +02:00
|
|
|
if (s->control & PARA_CTR_DIR)
|
|
|
|
ret = s->datar;
|
|
|
|
else
|
|
|
|
ret = s->dataw;
|
2005-01-15 13:02:56 +01:00
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_STS:
|
2007-06-07 23:07:11 +02:00
|
|
|
ret = s->status;
|
|
|
|
s->irq_pending = 0;
|
|
|
|
if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
|
|
|
|
/* XXX Fixme: wait 5 microseconds */
|
|
|
|
if (s->status & PARA_STS_ACK)
|
|
|
|
s->status &= ~PARA_STS_ACK;
|
|
|
|
else {
|
|
|
|
/* XXX Fixme: wait 5 microseconds */
|
|
|
|
s->status |= PARA_STS_ACK;
|
|
|
|
s->status |= PARA_STS_BUSY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
parallel_update_irq(s);
|
2005-01-15 13:02:56 +01:00
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_CTR:
|
2005-01-15 13:02:56 +01:00
|
|
|
ret = s->control;
|
|
|
|
break;
|
|
|
|
}
|
2007-02-18 00:44:43 +01:00
|
|
|
pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
|
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint8_t ret = 0xff;
|
|
|
|
addr &= 7;
|
|
|
|
switch(addr) {
|
|
|
|
case PARA_REG_DATA:
|
2007-06-07 23:07:11 +02:00
|
|
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
|
|
|
|
if (s->last_read_offset != addr || s->datar != ret)
|
|
|
|
pdebug("rd%02x\n", ret);
|
2007-02-18 00:44:43 +01:00
|
|
|
s->datar = ret;
|
|
|
|
break;
|
|
|
|
case PARA_REG_STS:
|
2007-06-07 23:07:11 +02:00
|
|
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
|
|
|
|
ret &= ~PARA_STS_TMOUT;
|
|
|
|
if (s->epp_timeout)
|
|
|
|
ret |= PARA_STS_TMOUT;
|
|
|
|
if (s->last_read_offset != addr || s->status != ret)
|
|
|
|
pdebug("rs%02x\n", ret);
|
|
|
|
s->status = ret;
|
2007-02-18 00:44:43 +01:00
|
|
|
break;
|
|
|
|
case PARA_REG_CTR:
|
|
|
|
/* s->control has some bits fixed to 1. It is zero only when
|
2007-06-07 23:07:11 +02:00
|
|
|
it has not been yet written to. */
|
|
|
|
if (s->control == 0) {
|
|
|
|
qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
|
|
|
|
if (s->last_read_offset != addr)
|
|
|
|
pdebug("rc%02x\n", ret);
|
|
|
|
s->control = ret;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
ret = s->control;
|
|
|
|
if (s->last_read_offset != addr)
|
|
|
|
pdebug("rc%02x\n", ret);
|
|
|
|
}
|
2007-02-18 00:44:43 +01:00
|
|
|
break;
|
|
|
|
case PARA_REG_EPP_ADDR:
|
2007-06-07 23:07:11 +02:00
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
|
|
|
/* Controls not correct for EPP addr cycle, so do nothing */
|
|
|
|
pdebug("ra%02x s\n", ret);
|
|
|
|
else {
|
|
|
|
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
|
|
|
|
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
|
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("ra%02x t\n", ret);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
pdebug("ra%02x\n", ret);
|
|
|
|
}
|
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
case PARA_REG_EPP_DATA:
|
2007-06-07 23:07:11 +02:00
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
|
|
|
|
/* Controls not correct for EPP data cycle, so do nothing */
|
|
|
|
pdebug("re%02x s\n", ret);
|
|
|
|
else {
|
|
|
|
struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
|
|
|
|
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
|
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("re%02x t\n", ret);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
pdebug("re%02x\n", ret);
|
|
|
|
}
|
|
|
|
break;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
s->last_read_offset = addr;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
|
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint32_t ret;
|
|
|
|
uint16_t eppdata = ~0;
|
|
|
|
int err;
|
|
|
|
struct ParallelIOArg ioarg = {
|
2007-06-07 23:07:11 +02:00
|
|
|
.buffer = &eppdata, .count = sizeof(eppdata)
|
2007-02-18 00:44:43 +01:00
|
|
|
};
|
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
2007-06-07 23:07:11 +02:00
|
|
|
/* Controls not correct for EPP data cycle, so do nothing */
|
|
|
|
pdebug("re%04x s\n", eppdata);
|
|
|
|
return eppdata;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
|
|
|
|
ret = le16_to_cpu(eppdata);
|
|
|
|
|
|
|
|
if (err) {
|
2007-06-07 23:07:11 +02:00
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("re%04x t\n", ret);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
else
|
2007-06-07 23:07:11 +02:00
|
|
|
pdebug("re%04x\n", ret);
|
2007-02-18 00:44:43 +01:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
|
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
uint32_t ret;
|
|
|
|
uint32_t eppdata = ~0U;
|
|
|
|
int err;
|
|
|
|
struct ParallelIOArg ioarg = {
|
2007-06-07 23:07:11 +02:00
|
|
|
.buffer = &eppdata, .count = sizeof(eppdata)
|
2007-02-18 00:44:43 +01:00
|
|
|
};
|
|
|
|
if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
|
2007-06-07 23:07:11 +02:00
|
|
|
/* Controls not correct for EPP data cycle, so do nothing */
|
|
|
|
pdebug("re%08x s\n", eppdata);
|
|
|
|
return eppdata;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
|
|
|
|
ret = le32_to_cpu(eppdata);
|
|
|
|
|
|
|
|
if (err) {
|
2007-06-07 23:07:11 +02:00
|
|
|
s->epp_timeout = 1;
|
|
|
|
pdebug("re%08x t\n", ret);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
else
|
2007-06-07 23:07:11 +02:00
|
|
|
pdebug("re%08x\n", ret);
|
2007-02-18 00:44:43 +01:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
|
|
|
|
{
|
2010-04-25 20:58:25 +02:00
|
|
|
pdebug("wecp%d=%02x\n", addr & 7, val);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
|
|
|
|
{
|
|
|
|
uint8_t ret = 0xff;
|
2010-04-25 20:58:25 +02:00
|
|
|
|
|
|
|
pdebug("recp%d:%02x\n", addr & 7, ret);
|
2005-01-15 13:02:56 +01:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2008-12-08 00:26:09 +01:00
|
|
|
static void parallel_reset(void *opaque)
|
2005-01-15 13:02:56 +01:00
|
|
|
{
|
2008-12-08 00:26:09 +01:00
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2007-02-18 00:44:43 +01:00
|
|
|
s->datar = ~0;
|
|
|
|
s->dataw = ~0;
|
2005-01-15 13:02:56 +01:00
|
|
|
s->status = PARA_STS_BUSY;
|
|
|
|
s->status |= PARA_STS_ACK;
|
|
|
|
s->status |= PARA_STS_ONLINE;
|
|
|
|
s->status |= PARA_STS_ERROR;
|
2008-02-10 14:34:48 +01:00
|
|
|
s->status |= PARA_STS_TMOUT;
|
2005-01-15 13:02:56 +01:00
|
|
|
s->control = PARA_CTR_SELECT;
|
|
|
|
s->control |= PARA_CTR_INIT;
|
2008-02-10 14:34:48 +01:00
|
|
|
s->control |= 0xc0;
|
2007-02-18 00:44:43 +01:00
|
|
|
s->irq_pending = 0;
|
|
|
|
s->hw_driver = 0;
|
|
|
|
s->epp_timeout = 0;
|
|
|
|
s->last_read_offset = ~0U;
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2009-10-13 13:38:39 +02:00
|
|
|
static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
|
|
|
|
|
2009-09-22 13:53:22 +02:00
|
|
|
static int parallel_isa_initfn(ISADevice *dev)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
2009-10-13 13:38:39 +02:00
|
|
|
static int index;
|
2009-09-22 13:53:22 +02:00
|
|
|
ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
|
|
|
|
ParallelState *s = &isa->state;
|
2009-10-13 13:38:39 +02:00
|
|
|
int base;
|
2007-06-18 20:55:46 +02:00
|
|
|
uint8_t dummy;
|
|
|
|
|
2009-09-22 13:53:22 +02:00
|
|
|
if (!s->chr) {
|
|
|
|
fprintf(stderr, "Can't create parallel device, empty char device\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2009-10-13 13:38:39 +02:00
|
|
|
if (isa->index == -1)
|
|
|
|
isa->index = index;
|
|
|
|
if (isa->index >= MAX_PARALLEL_PORTS)
|
|
|
|
return -1;
|
|
|
|
if (isa->iobase == -1)
|
|
|
|
isa->iobase = isa_parallel_io[isa->index];
|
|
|
|
index++;
|
|
|
|
|
|
|
|
base = isa->iobase;
|
2009-09-22 13:53:22 +02:00
|
|
|
isa_init_irq(dev, &s->irq, isa->isairq);
|
2009-06-27 09:25:07 +02:00
|
|
|
qemu_register_reset(parallel_reset, s);
|
2005-01-15 13:02:56 +01:00
|
|
|
|
2009-09-22 13:53:22 +02:00
|
|
|
if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
|
2007-02-18 00:44:43 +01:00
|
|
|
s->hw_driver = 1;
|
2007-06-07 23:07:11 +02:00
|
|
|
s->status = dummy;
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (s->hw_driver) {
|
2007-06-07 23:07:11 +02:00
|
|
|
register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
|
|
|
|
register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
|
2010-12-08 12:34:56 +01:00
|
|
|
isa_init_ioport_range(dev, base, 8);
|
|
|
|
|
2007-06-07 23:07:11 +02:00
|
|
|
register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
|
|
|
|
register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
|
|
|
|
register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
|
|
|
|
register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
|
2010-12-08 12:34:56 +01:00
|
|
|
isa_init_ioport(dev, base+4);
|
2007-06-07 23:07:11 +02:00
|
|
|
register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
|
|
|
|
register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
|
2010-12-08 12:34:56 +01:00
|
|
|
isa_init_ioport_range(dev, base+0x400, 8);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
|
|
|
else {
|
2007-06-07 23:07:11 +02:00
|
|
|
register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
|
|
|
|
register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
|
2010-12-08 12:34:56 +01:00
|
|
|
isa_init_ioport_range(dev, base, 8);
|
2007-02-18 00:44:43 +01:00
|
|
|
}
|
2009-09-22 13:53:22 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-06-18 20:55:46 +02:00
|
|
|
/* Memory mapped interface */
|
2009-10-01 23:12:16 +02:00
|
|
|
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2008-12-01 19:59:50 +01:00
|
|
|
return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2007-11-18 02:44:38 +01:00
|
|
|
static void parallel_mm_writeb (void *opaque,
|
2009-10-01 23:12:16 +02:00
|
|
|
target_phys_addr_t addr, uint32_t value)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2008-12-01 19:59:50 +01:00
|
|
|
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2008-12-01 19:59:50 +01:00
|
|
|
return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2007-11-18 02:44:38 +01:00
|
|
|
static void parallel_mm_writew (void *opaque,
|
2009-10-01 23:12:16 +02:00
|
|
|
target_phys_addr_t addr, uint32_t value)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2008-12-01 19:59:50 +01:00
|
|
|
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2008-12-01 19:59:50 +01:00
|
|
|
return parallel_ioport_read_sw(s, addr >> s->it_shift);
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2007-11-18 02:44:38 +01:00
|
|
|
static void parallel_mm_writel (void *opaque,
|
2009-10-01 23:12:16 +02:00
|
|
|
target_phys_addr_t addr, uint32_t value)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s = opaque;
|
|
|
|
|
2008-12-01 19:59:50 +01:00
|
|
|
parallel_ioport_write_sw(s, addr >> s->it_shift, value);
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
|
|
|
|
2009-08-25 20:29:31 +02:00
|
|
|
static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
|
2007-06-18 20:55:46 +02:00
|
|
|
¶llel_mm_readb,
|
|
|
|
¶llel_mm_readw,
|
|
|
|
¶llel_mm_readl,
|
|
|
|
};
|
|
|
|
|
2009-08-25 20:29:31 +02:00
|
|
|
static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
|
2007-06-18 20:55:46 +02:00
|
|
|
¶llel_mm_writeb,
|
|
|
|
¶llel_mm_writew,
|
|
|
|
¶llel_mm_writel,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* If fd is zero, it means that the parallel device uses the console */
|
2011-02-05 15:51:57 +01:00
|
|
|
bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
|
|
|
|
CharDriverState *chr)
|
2007-06-18 20:55:46 +02:00
|
|
|
{
|
|
|
|
ParallelState *s;
|
|
|
|
int io_sw;
|
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
s = g_malloc0(sizeof(ParallelState));
|
2008-12-08 00:26:09 +01:00
|
|
|
s->irq = irq;
|
|
|
|
s->chr = chr;
|
2007-06-18 20:55:46 +02:00
|
|
|
s->it_shift = it_shift;
|
2009-06-27 09:25:07 +02:00
|
|
|
qemu_register_reset(parallel_reset, s);
|
2007-06-18 20:55:46 +02:00
|
|
|
|
2010-12-08 12:05:37 +01:00
|
|
|
io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw,
|
|
|
|
s, DEVICE_NATIVE_ENDIAN);
|
2007-06-18 20:55:46 +02:00
|
|
|
cpu_register_physical_memory(base, 8 << it_shift, io_sw);
|
2011-02-05 15:51:57 +01:00
|
|
|
return true;
|
2007-06-18 20:55:46 +02:00
|
|
|
}
|
2009-09-22 13:53:22 +02:00
|
|
|
|
|
|
|
static ISADeviceInfo parallel_isa_info = {
|
|
|
|
.qdev.name = "isa-parallel",
|
|
|
|
.qdev.size = sizeof(ISAParallelState),
|
|
|
|
.init = parallel_isa_initfn,
|
|
|
|
.qdev.props = (Property[]) {
|
2009-11-17 11:28:41 +01:00
|
|
|
DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
|
2009-10-13 13:38:39 +02:00
|
|
|
DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase, -1),
|
2009-09-22 13:53:22 +02:00
|
|
|
DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
|
|
|
|
DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static void parallel_register_devices(void)
|
|
|
|
{
|
|
|
|
isa_qdev_register(¶llel_isa_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
device_init(parallel_register_devices)
|