2008-02-01 11:05:41 +01:00
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-06-29 11:14:47 +02:00
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#ifndef I386_TCG_TARGET_H
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#define I386_TCG_TARGET_H
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2008-02-01 11:05:41 +01:00
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2014-04-01 17:34:03 +02:00
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#define TCG_TARGET_INSN_UNIT_SIZE 1
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2015-05-05 09:18:22 +02:00
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 31
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2014-04-01 17:34:03 +02:00
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2013-08-20 23:41:29 +02:00
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#ifdef __x86_64__
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# define TCG_TARGET_REG_BITS 64
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2017-08-17 23:47:43 +02:00
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# define TCG_TARGET_NB_REGS 32
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2010-06-04 02:35:17 +02:00
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#else
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2013-08-20 23:41:29 +02:00
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# define TCG_TARGET_REG_BITS 32
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2017-08-17 23:47:43 +02:00
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# define TCG_TARGET_NB_REGS 24
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2010-06-04 02:35:17 +02:00
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#endif
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2008-02-01 11:05:41 +01:00
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2011-11-09 09:03:33 +01:00
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typedef enum {
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2008-02-01 11:05:41 +01:00
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TCG_REG_EAX = 0,
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TCG_REG_ECX,
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TCG_REG_EDX,
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TCG_REG_EBX,
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TCG_REG_ESP,
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TCG_REG_EBP,
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TCG_REG_ESI,
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TCG_REG_EDI,
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2010-06-04 02:35:17 +02:00
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/* 64-bit registers; always define the symbols to avoid
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too much if-deffing. */
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_R15,
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2017-08-17 23:47:43 +02:00
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TCG_REG_XMM0,
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TCG_REG_XMM1,
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TCG_REG_XMM2,
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TCG_REG_XMM3,
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TCG_REG_XMM4,
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TCG_REG_XMM5,
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TCG_REG_XMM6,
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TCG_REG_XMM7,
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/* 64-bit registers; likewise always define. */
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TCG_REG_XMM8,
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TCG_REG_XMM9,
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TCG_REG_XMM10,
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TCG_REG_XMM11,
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TCG_REG_XMM12,
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TCG_REG_XMM13,
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TCG_REG_XMM14,
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TCG_REG_XMM15,
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2010-06-04 02:35:17 +02:00
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TCG_REG_RAX = TCG_REG_EAX,
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TCG_REG_RCX = TCG_REG_ECX,
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TCG_REG_RDX = TCG_REG_EDX,
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TCG_REG_RBX = TCG_REG_EBX,
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TCG_REG_RSP = TCG_REG_ESP,
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TCG_REG_RBP = TCG_REG_EBP,
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TCG_REG_RSI = TCG_REG_ESI,
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TCG_REG_RDI = TCG_REG_EDI,
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2018-10-30 22:52:44 +01:00
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TCG_AREG0 = TCG_REG_EBP,
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2018-10-30 22:55:43 +01:00
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TCG_REG_CALL_STACK = TCG_REG_ESP
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2011-11-09 09:03:33 +01:00
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} TCGReg;
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2008-02-01 11:05:41 +01:00
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 16
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2012-09-13 19:37:43 +02:00
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#if defined(_WIN64)
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#define TCG_TARGET_CALL_STACK_OFFSET 32
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#else
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2008-05-22 16:59:57 +02:00
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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2012-09-13 19:37:43 +02:00
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#endif
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2008-02-01 11:05:41 +01:00
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2014-01-28 06:49:17 +01:00
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extern bool have_bmi1;
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2016-11-22 14:15:04 +01:00
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extern bool have_popcnt;
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2017-08-17 23:47:43 +02:00
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extern bool have_avx1;
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extern bool have_avx2;
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2014-01-28 06:49:17 +01:00
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2009-03-10 20:37:46 +01:00
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/* optional instructions */
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2011-08-17 23:11:46 +02:00
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#define TCG_TARGET_HAS_div2_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 1
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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2014-01-28 06:49:17 +01:00
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#define TCG_TARGET_HAS_andc_i32 have_bmi1
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2011-08-17 23:11:46 +02:00
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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2016-11-16 12:22:54 +01:00
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#define TCG_TARGET_HAS_clz_i32 1
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#define TCG_TARGET_HAS_ctz_i32 1
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2016-11-22 14:15:04 +01:00
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#define TCG_TARGET_HAS_ctpop_i32 have_popcnt
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2011-09-29 18:52:11 +02:00
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#define TCG_TARGET_HAS_deposit_i32 1
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2016-10-14 21:08:13 +02:00
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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2012-09-21 19:13:36 +02:00
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#define TCG_TARGET_HAS_movcond_i32 1
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2013-02-20 08:51:50 +01:00
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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2013-02-20 08:51:57 +01:00
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#define TCG_TARGET_HAS_muls2_i32 1
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2013-08-14 23:35:56 +02:00
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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2017-04-27 05:29:18 +02:00
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#define TCG_TARGET_HAS_goto_ptr 1
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2017-08-01 07:02:31 +02:00
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#define TCG_TARGET_HAS_direct_jump 1
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2009-03-10 20:37:46 +01:00
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2010-06-04 02:35:17 +02:00
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#if TCG_TARGET_REG_BITS == 64
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2015-07-24 16:16:00 +02:00
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#define TCG_TARGET_HAS_extrl_i64_i32 0
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#define TCG_TARGET_HAS_extrh_i64_i32 0
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2011-08-17 23:11:46 +02:00
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#define TCG_TARGET_HAS_div2_i64 1
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#define TCG_TARGET_HAS_rot_i64 1
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#define TCG_TARGET_HAS_ext8s_i64 1
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#define TCG_TARGET_HAS_ext16s_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext8u_i64 1
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#define TCG_TARGET_HAS_ext16u_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_neg_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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2014-01-28 06:49:17 +01:00
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#define TCG_TARGET_HAS_andc_i64 have_bmi1
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2011-08-17 23:11:46 +02:00
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_nor_i64 0
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2016-11-16 12:22:54 +01:00
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#define TCG_TARGET_HAS_clz_i64 1
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#define TCG_TARGET_HAS_ctz_i64 1
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2016-11-22 14:15:04 +01:00
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#define TCG_TARGET_HAS_ctpop_i64 have_popcnt
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2011-09-29 18:52:11 +02:00
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#define TCG_TARGET_HAS_deposit_i64 1
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2016-10-14 21:08:13 +02:00
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#define TCG_TARGET_HAS_extract_i64 1
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2016-10-14 19:04:32 +02:00
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#define TCG_TARGET_HAS_sextract_i64 0
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2012-09-21 19:13:36 +02:00
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#define TCG_TARGET_HAS_movcond_i64 1
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2013-02-20 08:51:57 +01:00
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 1
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#define TCG_TARGET_HAS_muls2_i64 1
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2013-08-14 23:35:56 +02:00
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#define TCG_TARGET_HAS_muluh_i64 0
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#define TCG_TARGET_HAS_mulsh_i64 0
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2010-06-04 02:35:17 +02:00
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#endif
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2017-08-17 23:47:43 +02:00
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/* We do not support older SSE systems, only beginning with AVX1. */
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#define TCG_TARGET_HAS_v64 have_avx1
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#define TCG_TARGET_HAS_v128 have_avx1
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#define TCG_TARGET_HAS_v256 have_avx2
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec 0
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#define TCG_TARGET_HAS_not_vec 0
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#define TCG_TARGET_HAS_neg_vec 0
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 0
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#define TCG_TARGET_HAS_shv_vec 0
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#define TCG_TARGET_HAS_cmp_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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2011-09-29 18:52:11 +02:00
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
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((ofs) == 0 && (len) == 16))
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#define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid
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2016-10-14 21:08:13 +02:00
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/* Check for the possibility of high-byte extraction and, for 64-bit,
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zero-extending 32-bit right-shift. */
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#define TCG_TARGET_extract_i32_valid(ofs, len) ((ofs) == 8 && (len) == 8)
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#define TCG_TARGET_extract_i64_valid(ofs, len) \
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(((ofs) == 8 && (len) == 8) || ((ofs) + (len)) == 32)
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2013-08-20 23:22:50 +02:00
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static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
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2008-02-01 11:05:41 +01:00
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{
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}
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2012-12-06 12:15:58 +01:00
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2017-08-01 07:02:31 +02:00
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static inline void tb_target_set_jmp_target(uintptr_t tc_ptr,
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uintptr_t jmp_addr, uintptr_t addr)
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{
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/* patch the branch destination */
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atomic_set((int32_t *)jmp_addr, addr - (jmp_addr + 4));
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/* no need to flush icache explicitly */
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}
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2017-02-23 19:29:27 +01:00
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/* This defines the natural memory order supported by this
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* architecture before guarantees made by various barrier
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* instructions.
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*
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* The x86 has a pretty strong memory ordering which only really
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* allows for some stores to be re-ordered after loads.
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*/
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#include "tcg-mo.h"
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#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
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2017-07-30 21:30:41 +02:00
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#ifdef CONFIG_SOFTMMU
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#define TCG_TARGET_NEED_LDST_LABELS
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#endif
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2017-07-21 07:56:42 +02:00
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#define TCG_TARGET_NEED_POOL_LABELS
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2017-07-30 21:30:41 +02:00
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2012-12-06 12:15:58 +01:00
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#endif
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