2012-07-20 09:50:39 +02:00
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/*
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* OpenRISC MMU.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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* Zhizhou Zhang <etouzh@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2016-01-26 19:17:22 +01:00
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#include "qemu/osdep.h"
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2012-07-20 09:50:39 +02:00
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#include "cpu.h"
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2016-03-15 13:18:37 +01:00
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#include "exec/exec-all.h"
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2012-07-20 09:50:39 +02:00
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#include "qemu-common.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/gdbstub.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/host-utils.h"
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2012-07-20 09:50:39 +02:00
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#endif
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2012-07-20 09:50:40 +02:00
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#ifndef CONFIG_USER_ONLY
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2018-05-23 01:51:19 +02:00
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static inline int get_phys_nommu(hwaddr *physical, int *prot,
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target_ulong address)
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2012-07-20 09:50:40 +02:00
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{
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*physical = address;
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2013-10-22 02:12:39 +02:00
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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2012-07-20 09:50:40 +02:00
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return TLBRET_MATCH;
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}
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2018-05-23 01:51:19 +02:00
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static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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target_ulong address, int rw, bool supervisor)
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2012-07-20 09:50:40 +02:00
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{
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int vpn = address >> TARGET_PAGE_BITS;
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2018-05-23 05:18:20 +02:00
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int idx = vpn & TLB_MASK;
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2012-07-20 09:50:40 +02:00
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int right = 0;
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2018-05-23 04:36:27 +02:00
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uint32_t mr = cpu->env.tlb.itlb[idx].mr;
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uint32_t tr = cpu->env.tlb.itlb[idx].tr;
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2012-07-20 09:50:40 +02:00
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2018-05-23 04:36:27 +02:00
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if ((mr >> TARGET_PAGE_BITS) != vpn) {
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2012-07-20 09:50:40 +02:00
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return TLBRET_NOMATCH;
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}
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2018-05-23 04:36:27 +02:00
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if (!(mr & 1)) {
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2012-07-20 09:50:40 +02:00
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return TLBRET_INVALID;
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}
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2018-05-23 01:51:19 +02:00
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if (supervisor) {
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2018-05-23 04:36:27 +02:00
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if (tr & SXE) {
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2012-07-20 09:50:40 +02:00
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right |= PAGE_EXEC;
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}
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} else {
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2018-05-23 04:36:27 +02:00
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if (tr & UXE) {
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2012-07-20 09:50:40 +02:00
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right |= PAGE_EXEC;
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}
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}
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if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
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return TLBRET_BADADDR;
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}
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2018-05-23 04:36:27 +02:00
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*physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
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2012-07-20 09:50:40 +02:00
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*prot = right;
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return TLBRET_MATCH;
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}
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2018-05-23 01:51:19 +02:00
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static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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target_ulong address, int rw, bool supervisor)
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2012-07-20 09:50:40 +02:00
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{
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int vpn = address >> TARGET_PAGE_BITS;
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2018-05-23 05:18:20 +02:00
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int idx = vpn & TLB_MASK;
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2012-07-20 09:50:40 +02:00
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int right = 0;
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2018-05-23 04:36:27 +02:00
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uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
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uint32_t tr = cpu->env.tlb.dtlb[idx].tr;
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2012-07-20 09:50:40 +02:00
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2018-05-23 04:36:27 +02:00
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if ((mr >> TARGET_PAGE_BITS) != vpn) {
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2012-07-20 09:50:40 +02:00
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return TLBRET_NOMATCH;
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}
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2018-05-23 04:36:27 +02:00
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if (!(mr & 1)) {
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2012-07-20 09:50:40 +02:00
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return TLBRET_INVALID;
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}
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2018-05-23 01:51:19 +02:00
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if (supervisor) {
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2018-05-23 04:36:27 +02:00
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if (tr & SRE) {
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2012-07-20 09:50:40 +02:00
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right |= PAGE_READ;
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}
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2018-05-23 04:36:27 +02:00
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if (tr & SWE) {
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2012-07-20 09:50:40 +02:00
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right |= PAGE_WRITE;
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}
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} else {
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2018-05-23 04:36:27 +02:00
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if (tr & URE) {
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2012-07-20 09:50:40 +02:00
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right |= PAGE_READ;
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}
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2018-05-23 04:36:27 +02:00
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if (tr & UWE) {
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2012-07-20 09:50:40 +02:00
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right |= PAGE_WRITE;
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}
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}
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2013-10-03 10:04:46 +02:00
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if (!(rw & 1) && ((right & PAGE_READ) == 0)) {
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2012-07-20 09:50:40 +02:00
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return TLBRET_BADADDR;
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}
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if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
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return TLBRET_BADADDR;
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}
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2018-05-23 04:36:27 +02:00
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*physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
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2012-07-20 09:50:40 +02:00
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*prot = right;
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return TLBRET_MATCH;
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}
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2018-05-23 01:51:19 +02:00
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static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical,
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int *prot, target_ulong address, int rw)
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2012-07-20 09:50:40 +02:00
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{
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2018-05-23 01:51:19 +02:00
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bool supervisor = (cpu->env.sr & SR_SM) != 0;
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int ret;
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/* Assume nommu results for a moment. */
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ret = get_phys_nommu(physical, prot, address);
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/* Overwrite with TLB lookup if enabled. */
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if (rw == MMU_INST_FETCH) {
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if (cpu->env.sr & SR_IME) {
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ret = get_phys_code(cpu, physical, prot, address, rw, supervisor);
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}
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} else {
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if (cpu->env.sr & SR_DME) {
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ret = get_phys_data(cpu, physical, prot, address, rw, supervisor);
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}
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2012-07-20 09:50:40 +02:00
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}
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return ret;
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}
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#endif
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static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
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target_ulong address,
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int rw, int tlb_error)
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{
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2013-08-26 08:31:06 +02:00
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CPUState *cs = CPU(cpu);
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2012-07-20 09:50:40 +02:00
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int exception = 0;
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switch (tlb_error) {
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default:
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if (rw == 2) {
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exception = EXCP_IPF;
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} else {
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exception = EXCP_DPF;
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}
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break;
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#ifndef CONFIG_USER_ONLY
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case TLBRET_BADADDR:
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if (rw == 2) {
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exception = EXCP_IPF;
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} else {
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exception = EXCP_DPF;
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}
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break;
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case TLBRET_INVALID:
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case TLBRET_NOMATCH:
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/* No TLB match for a mapped address */
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if (rw == 2) {
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exception = EXCP_ITLBMISS;
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} else {
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exception = EXCP_DTLBMISS;
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}
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break;
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#endif
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}
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2013-08-26 08:31:06 +02:00
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cs->exception_index = exception;
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2012-07-20 09:50:40 +02:00
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cpu->env.eear = address;
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2015-02-19 07:19:18 +01:00
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cpu->env.lock_addr = -1;
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2012-07-20 09:50:40 +02:00
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}
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#ifndef CONFIG_USER_ONLY
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2018-01-18 20:38:40 +01:00
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int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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2012-07-20 09:50:40 +02:00
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{
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2013-08-26 03:01:33 +02:00
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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2012-07-20 09:50:40 +02:00
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int ret = 0;
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2012-10-23 12:30:10 +02:00
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hwaddr physical = 0;
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2012-07-20 09:50:40 +02:00
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int prot = 0;
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2018-05-23 01:51:19 +02:00
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ret = get_phys_addr(cpu, &physical, &prot, address, rw);
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2012-07-20 09:50:40 +02:00
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if (ret == TLBRET_MATCH) {
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2013-09-03 13:59:37 +02:00
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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2013-10-22 02:12:39 +02:00
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physical & TARGET_PAGE_MASK, prot,
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2012-07-20 09:50:40 +02:00
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mmu_idx, TARGET_PAGE_SIZE);
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ret = 0;
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} else if (ret < 0) {
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cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
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ret = 1;
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}
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return ret;
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}
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#else
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2018-01-18 20:38:40 +01:00
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int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
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int rw, int mmu_idx)
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2012-07-20 09:50:40 +02:00
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{
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2013-08-26 03:01:33 +02:00
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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2012-07-20 09:50:40 +02:00
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int ret = 0;
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cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
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ret = 1;
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return ret;
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}
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#endif
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2012-07-20 09:50:39 +02:00
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#ifndef CONFIG_USER_ONLY
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2013-06-29 18:55:54 +02:00
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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2012-07-20 09:50:39 +02:00
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{
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2013-06-29 18:55:54 +02:00
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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2012-10-23 12:30:10 +02:00
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hwaddr phys_addr;
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2012-07-20 09:50:40 +02:00
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int prot;
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2017-03-13 15:53:29 +01:00
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int miss;
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2012-07-20 09:50:40 +02:00
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2017-03-13 15:53:29 +01:00
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/* Check memory for any kind of address, since during debug the
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gdb can ask for anything, check data tlb for address */
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2018-05-23 01:51:19 +02:00
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miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
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2017-03-13 15:53:29 +01:00
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/* Check instruction tlb */
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if (miss) {
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2018-05-23 01:51:19 +02:00
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miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH);
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2017-03-13 15:53:29 +01:00
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}
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/* Last, fall back to a plain address */
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if (miss) {
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2018-05-23 01:51:19 +02:00
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miss = get_phys_nommu(&phys_addr, &prot, addr);
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2012-07-20 09:50:40 +02:00
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}
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2017-03-13 15:53:29 +01:00
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if (miss) {
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return -1;
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} else {
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return phys_addr;
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}
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2012-07-20 09:50:39 +02:00
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}
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2018-05-23 03:21:21 +02:00
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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2018-05-23 04:51:00 +02:00
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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int ret, prot = 0;
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hwaddr physical = 0;
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if (mmu_idx == MMU_NOMMU_IDX) {
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ret = get_phys_nommu(&physical, &prot, addr);
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} else {
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bool super = mmu_idx == MMU_SUPERVISOR_IDX;
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if (access_type == MMU_INST_FETCH) {
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ret = get_phys_code(cpu, &physical, &prot, addr, 2, super);
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} else {
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ret = get_phys_data(cpu, &physical, &prot, addr,
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access_type == MMU_DATA_STORE, super);
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}
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}
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, addr & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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} else if (ret < 0) {
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int rw;
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if (access_type == MMU_INST_FETCH) {
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rw = 2;
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} else if (access_type == MMU_DATA_STORE) {
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rw = 1;
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} else {
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rw = 0;
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}
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cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret);
|
2018-05-23 03:21:21 +02:00
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/* Raise Exception. */
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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2012-07-20 09:50:39 +02:00
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#endif
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