2017-02-22 12:44:34 +01:00
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/*
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* PowerPC CPU routines for qemu.
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*
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* Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-19 08:11:26 +02:00
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* version 2.1 of the License, or (at your option) any later version.
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2017-02-22 12:44:34 +01:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu-models.h"
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2021-05-12 16:08:04 +02:00
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#include "cpu-qom.h"
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#include "exec/log.h"
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2021-05-12 16:08:03 +02:00
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#include "fpu/softfloat-helpers.h"
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2021-05-12 16:08:04 +02:00
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#include "mmu-hash64.h"
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2021-05-21 22:17:52 +02:00
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#include "helper_regs.h"
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2021-05-27 18:35:22 +02:00
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#include "sysemu/tcg.h"
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2017-02-22 12:44:34 +01:00
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target_ulong cpu_read_xer(CPUPPCState *env)
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{
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target/ppc: support for 32-bit carry and overflow
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme,
addze, and subfze always updates CA and CA32.
=> CA reflects the carry out of bit 0 in 64-bit mode and out of
bit 32 in 32-bit mode.
=> CA32 reflects the carry out of bit 32 independent of the
mode.
=> SO and OV reflects overflow of the 64-bit result in 64-bit
mode and overflow of the low-order 32-bit result in 32-bit
mode
=> OV32 reflects overflow of the low-order 32-bit independent of
the mode
* Multiply Low and Divide:
For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits
reflects overflow of the 64-bit result
For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits
reflects overflow of the 32-bit result
* Negate with OE=1 (nego)
For 64-bit mode if the register RA contains
0x8000_0000_0000_0000, OV and OV32 are set to 1.
For 32-bit mode if the register RA contains 0x8000_0000, OV and
OV32 are set to 1.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 05:57:54 +01:00
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if (is_isa300(env)) {
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return env->xer | (env->so << XER_SO) |
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(env->ov << XER_OV) | (env->ca << XER_CA) |
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(env->ov32 << XER_OV32) | (env->ca32 << XER_CA32);
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}
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2017-02-22 12:44:34 +01:00
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return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) |
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(env->ca << XER_CA);
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}
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void cpu_write_xer(CPUPPCState *env, target_ulong xer)
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{
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env->so = (xer >> XER_SO) & 1;
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env->ov = (xer >> XER_OV) & 1;
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env->ca = (xer >> XER_CA) & 1;
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target/ppc: support for 32-bit carry and overflow
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme,
addze, and subfze always updates CA and CA32.
=> CA reflects the carry out of bit 0 in 64-bit mode and out of
bit 32 in 32-bit mode.
=> CA32 reflects the carry out of bit 32 independent of the
mode.
=> SO and OV reflects overflow of the 64-bit result in 64-bit
mode and overflow of the low-order 32-bit result in 32-bit
mode
=> OV32 reflects overflow of the low-order 32-bit independent of
the mode
* Multiply Low and Divide:
For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits
reflects overflow of the 64-bit result
For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits
reflects overflow of the 32-bit result
* Negate with OE=1 (nego)
For 64-bit mode if the register RA contains
0x8000_0000_0000_0000, OV and OV32 are set to 1.
For 32-bit mode if the register RA contains 0x8000_0000, OV and
OV32 are set to 1.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 05:57:54 +01:00
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/* write all the flags, while reading back check of isa300 */
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env->ov32 = (xer >> XER_OV32) & 1;
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env->ca32 = (xer >> XER_CA32) & 1;
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env->xer = xer & ~((1ul << XER_SO) |
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(1ul << XER_OV) | (1ul << XER_CA) |
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(1ul << XER_OV32) | (1ul << XER_CA32));
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2017-02-22 12:44:34 +01:00
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}
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2021-05-12 16:08:03 +02:00
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void ppc_store_vscr(CPUPPCState *env, uint32_t vscr)
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{
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env->vscr = vscr & ~(1u << VSCR_SAT);
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/* Which bit we set is completely arbitrary, but clear the rest. */
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env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);
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env->vscr_sat.u64[1] = 0;
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set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
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}
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uint32_t ppc_get_vscr(CPUPPCState *env)
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{
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uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
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return env->vscr | (sat << VSCR_SAT);
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}
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2021-05-12 16:08:04 +02:00
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2021-05-21 22:17:52 +02:00
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/* GDBstub can read and write MSR... */
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void ppc_store_msr(CPUPPCState *env, target_ulong value)
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{
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hreg_store_msr(env, value, 0);
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}
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void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
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/* The gtse bit affects hflags */
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hreg_compute_hflags(env);
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}
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2021-05-27 18:35:22 +02:00
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static inline void fpscr_set_rounding_mode(CPUPPCState *env)
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{
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int rnd_type;
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/* Set rounding mode */
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switch (fpscr_rn) {
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case 0:
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/* Best approximation (round to nearest) */
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rnd_type = float_round_nearest_even;
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break;
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case 1:
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/* Smaller magnitude (round toward zero) */
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rnd_type = float_round_to_zero;
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break;
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case 2:
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/* Round toward +infinite */
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rnd_type = float_round_up;
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break;
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default:
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case 3:
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/* Round toward -infinite */
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rnd_type = float_round_down;
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break;
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}
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set_float_rounding_mode(rnd_type, &env->fp_status);
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}
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void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
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{
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val &= ~(FP_VX | FP_FEX);
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if (val & FPSCR_IX) {
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val |= FP_VX;
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}
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if ((val >> FPSCR_XX) & (val >> FPSCR_XE) & 0x1f) {
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val |= FP_FEX;
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}
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env->fpscr = val;
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if (tcg_enabled()) {
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fpscr_set_rounding_mode(env);
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}
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}
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