2011-09-06 01:55:25 +02:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions are met:
|
|
|
|
* * Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
|
|
* documentation and/or other materials provided with the distribution.
|
|
|
|
* * Neither the name of the Open Source and Linux Lab nor the
|
|
|
|
* names of its contributors may be used to endorse or promote products
|
|
|
|
* derived from this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
|
|
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
|
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
|
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
|
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
2016-01-26 19:17:21 +01:00
|
|
|
#include "qemu/osdep.h"
|
2011-09-06 01:55:25 +02:00
|
|
|
#include "cpu.h"
|
2012-12-17 18:19:49 +01:00
|
|
|
#include "exec/exec-all.h"
|
|
|
|
#include "exec/gdbstub.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/host-utils.h"
|
2011-09-06 01:55:25 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
#include "hw/loader.h"
|
|
|
|
#endif
|
|
|
|
|
2011-10-16 00:56:04 +02:00
|
|
|
static struct XtensaConfigList *xtensa_cores;
|
|
|
|
|
2013-07-07 01:47:51 +02:00
|
|
|
static void xtensa_core_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
2013-06-28 23:18:47 +02:00
|
|
|
CPUClass *cc = CPU_CLASS(oc);
|
2013-07-07 01:47:51 +02:00
|
|
|
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
|
|
|
|
const XtensaConfig *config = data;
|
|
|
|
|
|
|
|
xcc->config = config;
|
2013-06-28 23:18:47 +02:00
|
|
|
|
|
|
|
/* Use num_core_regs to see only non-privileged registers in an unmodified
|
|
|
|
* gdb. Use num_regs to see all registers. gdb modification is required
|
|
|
|
* for that: reset bit 0 in the 'flags' field of the registers definitions
|
|
|
|
* in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
|
|
|
|
*/
|
|
|
|
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
|
2013-07-07 01:47:51 +02:00
|
|
|
}
|
|
|
|
|
2017-11-04 03:44:46 +01:00
|
|
|
static void init_libisa(XtensaConfig *config)
|
|
|
|
{
|
|
|
|
unsigned i, j;
|
|
|
|
unsigned opcodes;
|
2018-08-28 06:43:43 +02:00
|
|
|
unsigned formats;
|
2017-11-04 03:44:46 +01:00
|
|
|
|
|
|
|
config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL);
|
|
|
|
assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH);
|
|
|
|
opcodes = xtensa_isa_num_opcodes(config->isa);
|
2018-08-28 06:43:43 +02:00
|
|
|
formats = xtensa_isa_num_formats(config->isa);
|
2017-11-04 03:44:46 +01:00
|
|
|
config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes);
|
|
|
|
|
2018-08-28 06:43:43 +02:00
|
|
|
for (i = 0; i < formats; ++i) {
|
|
|
|
assert(xtensa_format_num_slots(config->isa, i) <= MAX_INSN_SLOTS);
|
|
|
|
}
|
|
|
|
|
2017-11-04 03:44:46 +01:00
|
|
|
for (i = 0; i < opcodes; ++i) {
|
|
|
|
const char *opc_name = xtensa_opcode_name(config->isa, i);
|
|
|
|
XtensaOpcodeOps *ops = NULL;
|
|
|
|
|
|
|
|
assert(xtensa_opcode_num_operands(config->isa, i) <= MAX_OPCODE_ARGS);
|
|
|
|
if (!config->opcode_translators) {
|
|
|
|
ops = xtensa_find_opcode_ops(&xtensa_core_opcodes, opc_name);
|
|
|
|
} else {
|
|
|
|
for (j = 0; !ops && config->opcode_translators[j]; ++j) {
|
|
|
|
ops = xtensa_find_opcode_ops(config->opcode_translators[j],
|
|
|
|
opc_name);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
|
|
if (ops == NULL) {
|
|
|
|
fprintf(stderr,
|
|
|
|
"opcode translator not found for %s's opcode '%s'\n",
|
|
|
|
config->name, opc_name);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
config->opcode_ops[i] = ops;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-07-01 12:00:29 +02:00
|
|
|
void xtensa_finalize_config(XtensaConfig *config)
|
|
|
|
{
|
2017-11-04 03:44:46 +01:00
|
|
|
if (config->isa_internal) {
|
|
|
|
init_libisa(config);
|
|
|
|
}
|
2015-07-01 12:00:29 +02:00
|
|
|
|
2018-02-04 08:55:06 +01:00
|
|
|
if (config->gdb_regmap.num_regs == 0 ||
|
|
|
|
config->gdb_regmap.num_core_regs == 0) {
|
|
|
|
unsigned n_regs = 0;
|
|
|
|
unsigned n_core_regs = 0;
|
|
|
|
|
2018-08-16 19:34:56 +02:00
|
|
|
xtensa_count_regs(config, &n_regs, &n_core_regs);
|
2018-02-04 08:55:06 +01:00
|
|
|
if (config->gdb_regmap.num_regs == 0) {
|
|
|
|
config->gdb_regmap.num_regs = n_regs;
|
|
|
|
}
|
|
|
|
if (config->gdb_regmap.num_core_regs == 0) {
|
|
|
|
config->gdb_regmap.num_core_regs = n_core_regs;
|
|
|
|
}
|
2015-07-01 12:00:29 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-10-16 00:56:04 +02:00
|
|
|
void xtensa_register_core(XtensaConfigList *node)
|
|
|
|
{
|
2013-07-07 01:47:51 +02:00
|
|
|
TypeInfo type = {
|
|
|
|
.parent = TYPE_XTENSA_CPU,
|
|
|
|
.class_init = xtensa_core_class_init,
|
|
|
|
.class_data = (void *)node->config,
|
|
|
|
};
|
|
|
|
|
2011-10-16 00:56:04 +02:00
|
|
|
node->next = xtensa_cores;
|
|
|
|
xtensa_cores = node;
|
2017-10-05 15:50:58 +02:00
|
|
|
type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), node->config->name);
|
2013-07-07 01:47:51 +02:00
|
|
|
type_register(&type);
|
|
|
|
g_free((gpointer)type.name);
|
2011-10-16 00:56:04 +02:00
|
|
|
}
|
2011-09-06 01:55:27 +02:00
|
|
|
|
2012-03-14 01:38:23 +01:00
|
|
|
static uint32_t check_hw_breakpoints(CPUXtensaState *env)
|
2012-01-29 02:28:21 +01:00
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
|
|
|
for (i = 0; i < env->config->ndbreak; ++i) {
|
|
|
|
if (env->cpu_watchpoint[i] &&
|
|
|
|
env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
|
|
|
|
return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-12 15:06:48 +02:00
|
|
|
void xtensa_breakpoint_handler(CPUState *cs)
|
2012-01-29 02:28:21 +01:00
|
|
|
{
|
2014-09-12 15:06:48 +02:00
|
|
|
XtensaCPU *cpu = XTENSA_CPU(cs);
|
|
|
|
CPUXtensaState *env = &cpu->env;
|
2013-08-26 18:23:18 +02:00
|
|
|
|
|
|
|
if (cs->watchpoint_hit) {
|
|
|
|
if (cs->watchpoint_hit->flags & BP_CPU) {
|
2012-01-29 02:28:21 +01:00
|
|
|
uint32_t cause;
|
|
|
|
|
2013-08-26 18:23:18 +02:00
|
|
|
cs->watchpoint_hit = NULL;
|
2012-01-29 02:28:21 +01:00
|
|
|
cause = check_hw_breakpoints(env);
|
|
|
|
if (cause) {
|
|
|
|
debug_exception_env(env, cause);
|
|
|
|
}
|
2016-05-17 16:18:04 +02:00
|
|
|
cpu_loop_exit_noexc(cs);
|
2012-01-29 02:28:21 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-09-06 01:55:25 +02:00
|
|
|
void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
|
|
|
{
|
2011-10-16 00:56:04 +02:00
|
|
|
XtensaConfigList *core = xtensa_cores;
|
2011-09-06 01:55:27 +02:00
|
|
|
cpu_fprintf(f, "Available CPUs:\n");
|
2011-10-16 00:56:04 +02:00
|
|
|
for (; core; core = core->next) {
|
|
|
|
cpu_fprintf(f, " %s\n", core->config->name);
|
2011-09-06 01:55:27 +02:00
|
|
|
}
|
2011-09-06 01:55:25 +02:00
|
|
|
}
|
|
|
|
|
2017-01-25 19:54:11 +01:00
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
|
|
|
2012-03-14 01:38:23 +01:00
|
|
|
static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector)
|
2011-09-06 01:55:51 +02:00
|
|
|
{
|
|
|
|
if (xtensa_option_enabled(env->config,
|
|
|
|
XTENSA_OPTION_RELOCATABLE_VECTOR)) {
|
|
|
|
return vector - env->config->vecbase + env->sregs[VECBASE];
|
|
|
|
} else {
|
|
|
|
return vector;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-09-06 01:55:48 +02:00
|
|
|
/*!
|
|
|
|
* Handle penging IRQ.
|
|
|
|
* For the high priority interrupt jump to the corresponding interrupt vector.
|
|
|
|
* For the level-1 interrupt convert it to either user, kernel or double
|
|
|
|
* exception with the 'level-1 interrupt' exception cause.
|
|
|
|
*/
|
2012-03-14 01:38:23 +01:00
|
|
|
static void handle_interrupt(CPUXtensaState *env)
|
2011-09-06 01:55:48 +02:00
|
|
|
{
|
|
|
|
int level = env->pending_irq_level;
|
|
|
|
|
|
|
|
if (level > xtensa_get_cintlevel(env) &&
|
|
|
|
level <= env->config->nlevel &&
|
|
|
|
(env->config->level_mask[level] &
|
|
|
|
env->sregs[INTSET] &
|
|
|
|
env->sregs[INTENABLE])) {
|
2013-08-26 08:31:06 +02:00
|
|
|
CPUState *cs = CPU(xtensa_env_get_cpu(env));
|
|
|
|
|
2011-09-06 01:55:48 +02:00
|
|
|
if (level > 1) {
|
|
|
|
env->sregs[EPC1 + level - 1] = env->pc;
|
|
|
|
env->sregs[EPS2 + level - 2] = env->sregs[PS];
|
|
|
|
env->sregs[PS] =
|
|
|
|
(env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM;
|
2011-09-06 01:55:51 +02:00
|
|
|
env->pc = relocated_vector(env,
|
|
|
|
env->config->interrupt_vector[level]);
|
2011-09-06 01:55:48 +02:00
|
|
|
} else {
|
|
|
|
env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE;
|
|
|
|
|
|
|
|
if (env->sregs[PS] & PS_EXCM) {
|
|
|
|
if (env->config->ndepc) {
|
|
|
|
env->sregs[DEPC] = env->pc;
|
|
|
|
} else {
|
|
|
|
env->sregs[EPC1] = env->pc;
|
|
|
|
}
|
2013-08-26 08:31:06 +02:00
|
|
|
cs->exception_index = EXC_DOUBLE;
|
2011-09-06 01:55:48 +02:00
|
|
|
} else {
|
|
|
|
env->sregs[EPC1] = env->pc;
|
2013-08-26 08:31:06 +02:00
|
|
|
cs->exception_index =
|
2011-09-06 01:55:48 +02:00
|
|
|
(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
|
|
|
|
}
|
|
|
|
env->sregs[PS] |= PS_EXCM;
|
|
|
|
}
|
|
|
|
env->exception_taken = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-03-01 21:29:10 +01:00
|
|
|
/* Called from cpu_handle_interrupt with BQL held */
|
2013-02-02 10:57:51 +01:00
|
|
|
void xtensa_cpu_do_interrupt(CPUState *cs)
|
2011-09-06 01:55:25 +02:00
|
|
|
{
|
2013-02-02 10:57:51 +01:00
|
|
|
XtensaCPU *cpu = XTENSA_CPU(cs);
|
|
|
|
CPUXtensaState *env = &cpu->env;
|
|
|
|
|
2013-08-26 08:31:06 +02:00
|
|
|
if (cs->exception_index == EXC_IRQ) {
|
2011-09-06 01:55:48 +02:00
|
|
|
qemu_log_mask(CPU_LOG_INT,
|
|
|
|
"%s(EXC_IRQ) level = %d, cintlevel = %d, "
|
|
|
|
"pc = %08x, a0 = %08x, ps = %08x, "
|
|
|
|
"intset = %08x, intenable = %08x, "
|
|
|
|
"ccount = %08x\n",
|
|
|
|
__func__, env->pending_irq_level, xtensa_get_cintlevel(env),
|
|
|
|
env->pc, env->regs[0], env->sregs[PS],
|
|
|
|
env->sregs[INTSET], env->sregs[INTENABLE],
|
|
|
|
env->sregs[CCOUNT]);
|
|
|
|
handle_interrupt(env);
|
|
|
|
}
|
|
|
|
|
2013-08-26 08:31:06 +02:00
|
|
|
switch (cs->exception_index) {
|
2011-09-06 01:55:41 +02:00
|
|
|
case EXC_WINDOW_OVERFLOW4:
|
|
|
|
case EXC_WINDOW_UNDERFLOW4:
|
|
|
|
case EXC_WINDOW_OVERFLOW8:
|
|
|
|
case EXC_WINDOW_UNDERFLOW8:
|
|
|
|
case EXC_WINDOW_OVERFLOW12:
|
|
|
|
case EXC_WINDOW_UNDERFLOW12:
|
|
|
|
case EXC_KERNEL:
|
|
|
|
case EXC_USER:
|
|
|
|
case EXC_DOUBLE:
|
2012-01-13 06:21:32 +01:00
|
|
|
case EXC_DEBUG:
|
2011-09-06 01:55:48 +02:00
|
|
|
qemu_log_mask(CPU_LOG_INT, "%s(%d) "
|
|
|
|
"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
|
2013-08-26 08:31:06 +02:00
|
|
|
__func__, cs->exception_index,
|
2011-09-06 01:55:48 +02:00
|
|
|
env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
|
2013-08-26 08:31:06 +02:00
|
|
|
if (env->config->exception_vector[cs->exception_index]) {
|
2011-09-06 01:55:51 +02:00
|
|
|
env->pc = relocated_vector(env,
|
2013-08-26 08:31:06 +02:00
|
|
|
env->config->exception_vector[cs->exception_index]);
|
2011-09-06 01:55:41 +02:00
|
|
|
env->exception_taken = 1;
|
|
|
|
} else {
|
2015-11-13 13:43:35 +01:00
|
|
|
qemu_log_mask(CPU_LOG_INT, "%s(pc = %08x) bad exception_index: %d\n",
|
|
|
|
__func__, env->pc, cs->exception_index);
|
2011-09-06 01:55:41 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
2011-09-06 01:55:48 +02:00
|
|
|
case EXC_IRQ:
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
|
2013-08-26 08:31:06 +02:00
|
|
|
__func__, env->pc, cs->exception_index);
|
2011-09-06 01:55:48 +02:00
|
|
|
break;
|
2011-09-06 01:55:41 +02:00
|
|
|
}
|
2011-09-06 01:55:48 +02:00
|
|
|
check_interrupts(env);
|
2011-09-06 01:55:25 +02:00
|
|
|
}
|
2017-01-25 19:54:11 +01:00
|
|
|
#else
|
|
|
|
void xtensa_cpu_do_interrupt(CPUState *cs)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2011-09-06 01:55:53 +02:00
|
|
|
|
2014-09-13 18:45:18 +02:00
|
|
|
bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
|
|
{
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
|
|
cs->exception_index = EXC_IRQ;
|
|
|
|
xtensa_cpu_do_interrupt(cs);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-01-25 19:54:11 +01:00
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
|
|
|
|
|
|
int xtensa_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
|
|
|
|
int mmu_idx)
|
|
|
|
{
|
|
|
|
XtensaCPU *cpu = XTENSA_CPU(cs);
|
|
|
|
CPUXtensaState *env = &cpu->env;
|
|
|
|
|
|
|
|
qemu_log_mask(CPU_LOG_INT,
|
|
|
|
"%s: rw = %d, address = 0x%08" VADDR_PRIx ", size = %d\n",
|
|
|
|
__func__, rw, address, size);
|
|
|
|
env->sregs[EXCVADDR] = address;
|
|
|
|
env->sregs[EXCCAUSE] = rw ? STORE_PROHIBITED_CAUSE : LOAD_PROHIBITED_CAUSE;
|
|
|
|
cs->exception_index = EXC_USER;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
2016-12-14 03:52:08 +01:00
|
|
|
void xtensa_runstall(CPUXtensaState *env, bool runstall)
|
|
|
|
{
|
|
|
|
CPUState *cpu = CPU(xtensa_env_get_cpu(env));
|
|
|
|
|
|
|
|
env->runstall = runstall;
|
|
|
|
cpu->halted = runstall;
|
|
|
|
if (runstall) {
|
|
|
|
cpu_interrupt(cpu, CPU_INTERRUPT_HALT);
|
|
|
|
} else {
|
|
|
|
cpu_reset_interrupt(cpu, CPU_INTERRUPT_HALT);
|
|
|
|
}
|
|
|
|
}
|
2017-01-25 19:54:11 +01:00
|
|
|
#endif
|