2006-05-13 18:11:23 +02:00
|
|
|
/*
|
|
|
|
* QEMU PREP PCI host
|
|
|
|
*
|
|
|
|
* Copyright (c) 2006 Fabrice Bellard
|
2012-05-26 19:14:52 +02:00
|
|
|
* Copyright (c) 2011-2013 Andreas Färber
|
2007-09-16 23:08:06 +02:00
|
|
|
*
|
2006-05-13 18:11:23 +02:00
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
|
|
* in the Software without restriction, including without limitation the rights
|
|
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
|
|
* furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice shall be included in
|
|
|
|
* all copies or substantial portions of the Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
|
|
* THE SOFTWARE.
|
|
|
|
*/
|
|
|
|
|
2016-01-26 19:16:58 +01:00
|
|
|
#include "qemu/osdep.h"
|
2019-05-23 16:35:08 +02:00
|
|
|
#include "qemu-common.h"
|
2018-06-25 14:42:24 +02:00
|
|
|
#include "qemu/units.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/pci/pci.h"
|
|
|
|
#include "hw/pci/pci_bus.h"
|
|
|
|
#include "hw/pci/pci_host.h"
|
2019-08-12 07:23:51 +02:00
|
|
|
#include "hw/qdev-properties.h"
|
2019-08-12 07:23:45 +02:00
|
|
|
#include "migration/vmstate.h"
|
2019-12-12 17:15:43 +01:00
|
|
|
#include "hw/intc/i8259.h"
|
2019-08-12 07:23:42 +02:00
|
|
|
#include "hw/irq.h"
|
2013-11-05 00:09:45 +01:00
|
|
|
#include "hw/loader.h"
|
2018-09-08 11:08:19 +02:00
|
|
|
#include "hw/or-irq.h"
|
2012-12-17 18:19:49 +01:00
|
|
|
#include "exec/address-spaces.h"
|
2013-11-05 00:09:45 +01:00
|
|
|
#include "elf.h"
|
2020-09-03 22:43:22 +02:00
|
|
|
#include "qom/object.h"
|
2006-05-13 18:11:23 +02:00
|
|
|
|
2012-05-26 19:14:52 +02:00
|
|
|
#define TYPE_RAVEN_PCI_DEVICE "raven"
|
2012-08-20 19:08:04 +02:00
|
|
|
#define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
|
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
typedef struct RavenPCIState RavenPCIState;
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(RavenPCIState, RAVEN_PCI_DEVICE,
|
|
|
|
TYPE_RAVEN_PCI_DEVICE)
|
2012-05-26 19:14:52 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct RavenPCIState {
|
2012-05-26 19:14:52 +02:00
|
|
|
PCIDevice dev;
|
2013-11-05 00:09:45 +01:00
|
|
|
|
|
|
|
uint32_t elf_machine;
|
|
|
|
char *bios_name;
|
|
|
|
MemoryRegion bios;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2012-05-26 19:14:52 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
typedef struct PRePPCIState PREPPCIState;
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
|
|
|
|
TYPE_RAVEN_PCI_HOST_BRIDGE)
|
2012-08-20 19:08:04 +02:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct PRePPCIState {
|
2012-08-20 19:08:09 +02:00
|
|
|
PCIHostState parent_obj;
|
2012-08-20 19:08:04 +02:00
|
|
|
|
2018-09-08 11:08:19 +02:00
|
|
|
qemu_or_irq *or_irq;
|
2018-09-08 11:08:18 +02:00
|
|
|
qemu_irq pci_irqs[PCI_NUM_PINS];
|
2012-05-26 19:14:52 +02:00
|
|
|
PCIBus pci_bus;
|
2014-03-17 23:00:20 +01:00
|
|
|
AddressSpace pci_io_as;
|
2014-03-17 23:00:21 +01:00
|
|
|
MemoryRegion pci_io;
|
2014-03-17 23:00:20 +01:00
|
|
|
MemoryRegion pci_io_non_contiguous;
|
2014-03-17 23:00:22 +01:00
|
|
|
MemoryRegion pci_memory;
|
2014-03-17 23:00:19 +01:00
|
|
|
MemoryRegion pci_intack;
|
2014-03-17 23:00:23 +01:00
|
|
|
MemoryRegion bm;
|
|
|
|
MemoryRegion bm_ram_alias;
|
|
|
|
MemoryRegion bm_pci_memory_alias;
|
|
|
|
AddressSpace bm_as;
|
2012-05-26 19:14:52 +02:00
|
|
|
RavenPCIState pci_dev;
|
2014-03-17 23:00:20 +01:00
|
|
|
|
|
|
|
int contiguous_map;
|
2018-09-08 11:08:19 +02:00
|
|
|
bool is_legacy_prep;
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2006-05-13 18:11:23 +02:00
|
|
|
|
2018-06-25 14:42:24 +02:00
|
|
|
#define BIOS_SIZE (1 * MiB)
|
2013-11-05 00:09:45 +01:00
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static inline uint32_t raven_pci_io_config(hwaddr addr)
|
2006-05-13 18:11:23 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2012-08-20 19:08:04 +02:00
|
|
|
for (i = 0; i < 11; i++) {
|
|
|
|
if ((addr & (1 << (11 + i))) != 0) {
|
2006-05-13 18:11:23 +02:00
|
|
|
break;
|
2012-08-20 19:08:04 +02:00
|
|
|
}
|
2006-05-13 18:11:23 +02:00
|
|
|
}
|
|
|
|
return (addr & 0x7ff) | (i << 11);
|
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static void raven_pci_io_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned int size)
|
2006-05-13 18:11:23 +02:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
2012-08-20 19:08:09 +02:00
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
2014-03-17 23:00:25 +01:00
|
|
|
pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
|
2006-05-13 18:11:23 +02:00
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned int size)
|
2006-05-13 18:11:23 +02:00
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
2012-08-20 19:08:09 +02:00
|
|
|
PCIHostState *phb = PCI_HOST_BRIDGE(s);
|
2014-03-17 23:00:25 +01:00
|
|
|
return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
|
2006-05-13 18:11:23 +02:00
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static const MemoryRegionOps raven_pci_io_ops = {
|
|
|
|
.read = raven_pci_io_read,
|
|
|
|
.write = raven_pci_io_write,
|
2012-01-12 03:44:42 +01:00
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
2006-05-13 18:11:23 +02:00
|
|
|
};
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static uint64_t raven_intack_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned int size)
|
2012-04-14 22:48:37 +02:00
|
|
|
{
|
|
|
|
return pic_read_irq(isa_pic);
|
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static const MemoryRegionOps raven_intack_ops = {
|
|
|
|
.read = raven_intack_read,
|
2012-04-14 22:48:37 +02:00
|
|
|
.valid = {
|
|
|
|
.max_access_size = 1,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2014-03-17 23:00:20 +01:00
|
|
|
static inline hwaddr raven_io_address(PREPPCIState *s,
|
|
|
|
hwaddr addr)
|
|
|
|
{
|
|
|
|
if (s->contiguous_map == 0) {
|
|
|
|
/* 64 KB contiguous space for IOs */
|
|
|
|
addr &= 0xFFFF;
|
|
|
|
} else {
|
|
|
|
/* 8 MB non-contiguous space for IOs */
|
|
|
|
addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FIXME: handle endianness switch */
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t raven_io_read(void *opaque, hwaddr addr,
|
|
|
|
unsigned int size)
|
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
uint8_t buf[4];
|
|
|
|
|
|
|
|
addr = raven_io_address(s, addr);
|
2015-04-26 17:49:24 +02:00
|
|
|
address_space_read(&s->pci_io_as, addr + 0x80000000,
|
|
|
|
MEMTXATTRS_UNSPECIFIED, buf, size);
|
2014-03-17 23:00:20 +01:00
|
|
|
|
|
|
|
if (size == 1) {
|
|
|
|
return buf[0];
|
|
|
|
} else if (size == 2) {
|
2014-04-08 17:51:11 +02:00
|
|
|
return lduw_le_p(buf);
|
2014-03-17 23:00:20 +01:00
|
|
|
} else if (size == 4) {
|
2014-04-08 17:51:11 +02:00
|
|
|
return ldl_le_p(buf);
|
2014-03-17 23:00:20 +01:00
|
|
|
} else {
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void raven_io_write(void *opaque, hwaddr addr,
|
|
|
|
uint64_t val, unsigned int size)
|
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
uint8_t buf[4];
|
|
|
|
|
|
|
|
addr = raven_io_address(s, addr);
|
|
|
|
|
|
|
|
if (size == 1) {
|
|
|
|
buf[0] = val;
|
|
|
|
} else if (size == 2) {
|
2014-04-08 17:51:11 +02:00
|
|
|
stw_le_p(buf, val);
|
2014-03-17 23:00:20 +01:00
|
|
|
} else if (size == 4) {
|
2014-04-08 17:51:11 +02:00
|
|
|
stl_le_p(buf, val);
|
2014-03-17 23:00:20 +01:00
|
|
|
} else {
|
|
|
|
g_assert_not_reached();
|
|
|
|
}
|
|
|
|
|
2015-04-26 17:49:24 +02:00
|
|
|
address_space_write(&s->pci_io_as, addr + 0x80000000,
|
|
|
|
MEMTXATTRS_UNSPECIFIED, buf, size);
|
2014-03-17 23:00:20 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps raven_io_ops = {
|
|
|
|
.read = raven_io_read,
|
|
|
|
.write = raven_io_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.impl.max_access_size = 4,
|
|
|
|
.valid.unaligned = true,
|
|
|
|
};
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
|
2006-05-13 18:11:23 +02:00
|
|
|
{
|
2006-09-24 19:01:44 +02:00
|
|
|
return (irq_num + (pci_dev->devfn >> 3)) & 1;
|
2006-09-24 02:16:34 +02:00
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
static void raven_set_irq(void *opaque, int irq_num, int level)
|
2006-09-24 02:16:34 +02:00
|
|
|
{
|
2018-09-08 11:08:18 +02:00
|
|
|
PREPPCIState *s = opaque;
|
2009-08-28 15:28:17 +02:00
|
|
|
|
2018-09-08 11:08:18 +02:00
|
|
|
qemu_set_irq(s->pci_irqs[irq_num], level);
|
2006-05-13 18:11:23 +02:00
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:23 +01:00
|
|
|
static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
|
|
|
|
int devfn)
|
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
|
|
|
|
return &s->bm_as;
|
|
|
|
}
|
|
|
|
|
2014-03-17 23:00:20 +01:00
|
|
|
static void raven_change_gpio(void *opaque, int n, int level)
|
|
|
|
{
|
|
|
|
PREPPCIState *s = opaque;
|
|
|
|
|
|
|
|
s->contiguous_map = level;
|
|
|
|
}
|
|
|
|
|
2013-01-16 15:45:34 +01:00
|
|
|
static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
|
2006-05-13 18:11:23 +02:00
|
|
|
{
|
2013-01-16 15:45:34 +01:00
|
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(d);
|
2012-08-20 19:08:08 +02:00
|
|
|
PCIHostState *h = PCI_HOST_BRIDGE(dev);
|
2012-08-20 19:08:04 +02:00
|
|
|
PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
|
2012-01-03 02:42:46 +01:00
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
|
|
int i;
|
|
|
|
|
2018-09-08 11:08:19 +02:00
|
|
|
if (s->is_legacy_prep) {
|
|
|
|
for (i = 0; i < PCI_NUM_PINS; i++) {
|
|
|
|
sysbus_init_irq(dev, &s->pci_irqs[i]);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* According to PReP specification section 6.1.6 "System Interrupt
|
|
|
|
* Assignments", all PCI interrupts are routed via IRQ 15 */
|
|
|
|
s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
|
2018-09-08 11:08:19 +02:00
|
|
|
&error_fatal);
|
qdev: Convert bus-less devices to qdev_realize() with Coccinelle
All remaining conversions to qdev_realize() are for bus-less devices.
Coccinelle script:
// only correct for bus-less @dev!
@@
expression errp;
expression dev;
@@
- qdev_init_nofail(dev);
+ qdev_realize(dev, NULL, &error_fatal);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
@ depends on !(file in "hw/core/qdev.c") && !(file in "hw/core/bus.c")@
expression errp;
expression dev;
symbol true;
@@
- object_property_set_bool(dev, true, "realized", errp);
+ qdev_realize(DEVICE(dev), NULL, errp);
Note that Coccinelle chokes on ARMSSE typedef vs. macro in
hw/arm/armsse.c. Worked around by temporarily renaming the macro for
the spatch run.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-57-armbru@redhat.com>
2020-06-10 07:32:45 +02:00
|
|
|
qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
|
2018-09-08 11:08:19 +02:00
|
|
|
sysbus_init_irq(dev, &s->or_irq->out_irq);
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_PINS; i++) {
|
|
|
|
s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
|
|
|
|
}
|
2012-01-03 02:42:46 +01:00
|
|
|
}
|
2006-05-13 18:11:23 +02:00
|
|
|
|
2014-03-17 23:00:20 +01:00
|
|
|
qdev_init_gpio_in(d, raven_change_gpio, 1);
|
|
|
|
|
2018-09-08 11:08:18 +02:00
|
|
|
pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
|
2006-05-13 18:11:23 +02:00
|
|
|
|
2014-03-17 23:00:24 +01:00
|
|
|
memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
|
|
|
|
"pci-conf-idx", 4);
|
2014-03-17 23:00:21 +01:00
|
|
|
memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
|
2011-07-24 16:47:18 +02:00
|
|
|
|
2014-03-17 23:00:24 +01:00
|
|
|
memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
|
|
|
|
"pci-conf-data", 4);
|
2014-03-17 23:00:21 +01:00
|
|
|
memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
|
2006-05-13 18:11:23 +02:00
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
|
|
|
|
"pciio", 0x00400000);
|
2012-01-03 02:42:46 +01:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
|
2006-05-13 18:11:23 +02:00
|
|
|
|
2014-03-17 23:00:25 +01:00
|
|
|
memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
|
2014-03-17 23:00:19 +01:00
|
|
|
"pci-intack", 1);
|
|
|
|
memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
|
2012-01-03 01:50:07 +01:00
|
|
|
|
2012-05-26 19:14:52 +02:00
|
|
|
/* TODO Remove once realize propagates to child devices. */
|
2020-06-10 07:32:01 +02:00
|
|
|
qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
|
2012-05-26 19:14:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void raven_pcihost_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
PCIHostState *h = PCI_HOST_BRIDGE(obj);
|
|
|
|
PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
|
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
|
|
DeviceState *pci_dev;
|
|
|
|
|
2014-03-17 23:00:21 +01:00
|
|
|
memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
|
2014-03-17 23:00:20 +01:00
|
|
|
memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
|
|
|
|
"pci-io-non-contiguous", 0x00800000);
|
2014-04-01 23:19:15 +02:00
|
|
|
memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
|
2014-03-17 23:00:21 +01:00
|
|
|
address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
|
2014-03-17 23:00:20 +01:00
|
|
|
|
|
|
|
/* CPU address space */
|
2014-03-17 23:00:21 +01:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
|
2014-03-17 23:00:20 +01:00
|
|
|
memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
|
|
|
|
&s->pci_io_non_contiguous, 1);
|
2014-03-17 23:00:22 +01:00
|
|
|
memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
|
2017-11-29 09:46:22 +01:00
|
|
|
pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
|
|
|
|
&s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
|
2014-03-17 23:00:21 +01:00
|
|
|
|
2014-03-17 23:00:23 +01:00
|
|
|
/* Bus master address space */
|
2020-06-01 16:29:24 +02:00
|
|
|
memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
|
2014-03-17 23:00:23 +01:00
|
|
|
memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
|
|
|
|
&s->pci_memory, 0,
|
|
|
|
memory_region_size(&s->pci_memory));
|
|
|
|
memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
|
|
|
|
get_system_memory(), 0, 0x80000000);
|
|
|
|
memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
|
|
|
|
memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
|
|
|
|
address_space_init(&s->bm_as, &s->bm, "raven-bm");
|
|
|
|
pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
|
|
|
|
|
2012-05-26 19:14:52 +02:00
|
|
|
h->bus = &s->pci_bus;
|
|
|
|
|
2013-08-23 19:37:12 +02:00
|
|
|
object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
|
2012-05-26 19:14:52 +02:00
|
|
|
pci_dev = DEVICE(&s->pci_dev);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
|
2012-05-26 19:14:52 +02:00
|
|
|
NULL);
|
|
|
|
qdev_prop_set_bit(pci_dev, "multifunction", false);
|
2012-01-03 01:50:07 +01:00
|
|
|
}
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
static void raven_realize(PCIDevice *d, Error **errp)
|
2012-01-03 01:50:07 +01:00
|
|
|
{
|
2013-11-05 00:09:45 +01:00
|
|
|
RavenPCIState *s = RAVEN_PCI_DEVICE(d);
|
|
|
|
char *filename;
|
|
|
|
int bios_size = -1;
|
|
|
|
|
2006-05-13 18:11:23 +02:00
|
|
|
d->config[0x0C] = 0x08; // cache_line_size
|
|
|
|
d->config[0x0D] = 0x10; // latency_timer
|
|
|
|
d->config[0x34] = 0x00; // capabilities_pointer
|
|
|
|
|
2020-02-24 19:51:23 +01:00
|
|
|
memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
|
|
|
|
&error_fatal);
|
2013-11-05 00:09:45 +01:00
|
|
|
memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
|
|
|
|
&s->bios);
|
|
|
|
if (s->bios_name) {
|
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
|
|
|
|
if (filename) {
|
|
|
|
if (s->elf_machine != EM_NONE) {
|
2019-01-15 13:18:03 +01:00
|
|
|
bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
|
2020-01-26 23:55:04 +01:00
|
|
|
NULL, NULL, NULL, 1, s->elf_machine,
|
|
|
|
0, 0);
|
2013-11-05 00:09:45 +01:00
|
|
|
}
|
|
|
|
if (bios_size < 0) {
|
|
|
|
bios_size = get_image_size(filename);
|
|
|
|
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
|
|
|
|
hwaddr bios_addr;
|
|
|
|
bios_size = (bios_size + 0xfff) & ~0xfff;
|
|
|
|
bios_addr = (uint32_t)(-BIOS_SIZE);
|
|
|
|
bios_size = load_image_targphys(filename, bios_addr,
|
|
|
|
bios_size);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2017-02-09 12:14:41 +01:00
|
|
|
g_free(filename);
|
2013-11-05 00:09:45 +01:00
|
|
|
if (bios_size < 0 || bios_size > BIOS_SIZE) {
|
2017-02-09 12:14:41 +01:00
|
|
|
memory_region_del_subregion(get_system_memory(), &s->bios);
|
|
|
|
error_setg(errp, "Could not load bios image '%s'", s->bios_name);
|
|
|
|
return;
|
2013-11-05 00:09:45 +01:00
|
|
|
}
|
|
|
|
}
|
2017-02-09 12:14:41 +01:00
|
|
|
|
|
|
|
vmstate_register_ram_global(&s->bios);
|
2006-05-13 18:11:23 +02:00
|
|
|
}
|
2012-01-03 01:50:07 +01:00
|
|
|
|
|
|
|
static const VMStateDescription vmstate_raven = {
|
|
|
|
.name = "raven",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_PCI_DEVICE(dev, RavenPCIState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void raven_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
k->realize = raven_realize;
|
2011-12-04 19:22:06 +01:00
|
|
|
k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
|
|
|
|
k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
|
|
|
|
k->revision = 0x00;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->desc = "PReP Host Bridge - Motorola Raven";
|
|
|
|
dc->vmsd = &vmstate_raven;
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
/*
|
2015-12-17 17:35:13 +01:00
|
|
|
* Reason: PCI-facing part of the host bridge, not usable without
|
|
|
|
* the host-facing part, which can't be device_add'ed, yet.
|
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-11-28 17:26:58 +01:00
|
|
|
*/
|
2017-05-03 22:35:44 +02:00
|
|
|
dc->user_creatable = false;
|
2011-12-04 19:22:06 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo raven_info = {
|
2012-05-26 19:14:52 +02:00
|
|
|
.name = TYPE_RAVEN_PCI_DEVICE,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(RavenPCIState),
|
2011-12-04 19:22:06 +01:00
|
|
|
.class_init = raven_class_init,
|
2017-09-27 21:56:34 +02:00
|
|
|
.interfaces = (InterfaceInfo[]) {
|
|
|
|
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
|
|
|
|
{ },
|
|
|
|
},
|
2012-01-03 01:50:07 +01:00
|
|
|
};
|
|
|
|
|
2013-11-05 00:09:45 +01:00
|
|
|
static Property raven_pcihost_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
|
|
|
|
EM_NONE),
|
|
|
|
DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
|
2018-09-08 11:08:19 +02:00
|
|
|
/* Temporary workaround until legacy prep machine is removed */
|
|
|
|
DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
|
|
|
|
false),
|
2013-11-05 00:09:45 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void raven_pcihost_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
2013-01-16 15:45:34 +01:00
|
|
|
dc->realize = raven_pcihost_realizefn;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, raven_pcihost_properties);
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->fw_name = "pci";
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2012-08-20 19:07:56 +02:00
|
|
|
static const TypeInfo raven_pcihost_info = {
|
2012-08-20 19:08:04 +02:00
|
|
|
.name = TYPE_RAVEN_PCI_HOST_BRIDGE,
|
2012-08-20 19:08:08 +02:00
|
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
2011-12-08 04:34:16 +01:00
|
|
|
.instance_size = sizeof(PREPPCIState),
|
2012-05-26 19:14:52 +02:00
|
|
|
.instance_init = raven_pcihost_initfn,
|
2012-01-24 20:12:29 +01:00
|
|
|
.class_init = raven_pcihost_class_init,
|
2012-01-03 02:42:46 +01:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void raven_register_types(void)
|
2012-01-03 01:50:07 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&raven_pcihost_info);
|
|
|
|
type_register_static(&raven_info);
|
2012-01-03 01:50:07 +01:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(raven_register_types)
|