2016-06-29 13:47:03 +02:00
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#ifndef OPENPIC_H
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#define OPENPIC_H
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2009-03-02 17:42:04 +01:00
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2018-02-28 21:32:40 +01:00
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#include "hw/sysbus.h"
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2019-07-09 17:20:52 +02:00
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#include "hw/core/cpu.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2013-04-15 15:19:32 +02:00
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2018-02-28 21:32:40 +01:00
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#define MAX_CPU 32
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#define MAX_MSI 8
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#define VID 0x03 /* MPIC version ID */
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2013-06-18 03:58:07 +02:00
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2009-03-02 17:42:04 +01:00
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/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
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enum {
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OPENPIC_OUTPUT_INT = 0, /* IRQ */
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OPENPIC_OUTPUT_CINT, /* critical IRQ */
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OPENPIC_OUTPUT_MCK, /* Machine check event */
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OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
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OPENPIC_OUTPUT_RESET, /* Core reset event */
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OPENPIC_OUTPUT_NB,
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};
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2018-11-27 14:06:22 +01:00
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typedef struct IrqLines { qemu_irq irq[OPENPIC_OUTPUT_NB]; } IrqLines;
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2012-12-08 05:17:14 +01:00
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#define OPENPIC_MODEL_FSL_MPIC_20 1
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2013-01-21 16:53:53 +01:00
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#define OPENPIC_MODEL_FSL_MPIC_42 2
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2017-09-17 19:15:46 +02:00
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#define OPENPIC_MODEL_KEYLARGO 3
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2012-12-07 23:51:09 +01:00
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2013-04-15 15:19:32 +02:00
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#define OPENPIC_MAX_SRC 256
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#define OPENPIC_MAX_TMR 4
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#define OPENPIC_MAX_IPI 4
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#define OPENPIC_MAX_IRQ (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
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OPENPIC_MAX_TMR)
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2018-02-28 21:32:40 +01:00
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/* KeyLargo */
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#define KEYLARGO_MAX_CPU 4
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#define KEYLARGO_MAX_EXT 64
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#define KEYLARGO_MAX_IPI 4
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#define KEYLARGO_MAX_IRQ (64 + KEYLARGO_MAX_IPI)
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#define KEYLARGO_MAX_TMR 0
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#define KEYLARGO_IPI_IRQ (KEYLARGO_MAX_EXT) /* First IPI IRQ */
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/* Timers don't exist but this makes the code happy... */
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#define KEYLARGO_TMR_IRQ (KEYLARGO_IPI_IRQ + KEYLARGO_MAX_IPI)
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typedef struct FslMpicInfo {
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int max_ext;
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} FslMpicInfo;
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typedef enum IRQType {
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IRQ_TYPE_NORMAL = 0,
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IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
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IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
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} IRQType;
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2021-09-18 05:26:53 +02:00
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/*
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* Round up to the nearest 64 IRQs so that the queue length
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2018-02-28 21:32:40 +01:00
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* won't change when moving between 32 and 64 bit hosts.
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*/
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#define IRQQUEUE_SIZE_BITS ((OPENPIC_MAX_IRQ + 63) & ~63)
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typedef struct IRQQueue {
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unsigned long *queue;
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int32_t queue_size; /* Only used for VMSTATE_BITMAP */
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int next;
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int priority;
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} IRQQueue;
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typedef struct IRQSource {
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uint32_t ivpr; /* IRQ vector/priority register */
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uint32_t idr; /* IRQ destination register */
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uint32_t destmask; /* bitmap of CPU destinations */
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int last_cpu;
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int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
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int pending; /* TRUE if IRQ is pending */
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IRQType type;
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bool level:1; /* level-triggered */
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bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
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} IRQSource;
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#define IVPR_MASK_SHIFT 31
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#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
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#define IVPR_ACTIVITY_SHIFT 30
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#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
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#define IVPR_MODE_SHIFT 29
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#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
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#define IVPR_POLARITY_SHIFT 23
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#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
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#define IVPR_SENSE_SHIFT 22
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#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
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#define IVPR_PRIORITY_MASK (0xFU << 16)
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#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
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#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
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/* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
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#define IDR_EP 0x80000000 /* external pin */
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#define IDR_CI 0x40000000 /* critical interrupt */
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typedef struct OpenPICTimer {
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uint32_t tccr; /* Global timer current count register */
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uint32_t tbcr; /* Global timer base count register */
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int n_IRQ;
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bool qemu_timer_active; /* Is the qemu_timer is running? */
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struct QEMUTimer *qemu_timer;
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struct OpenPICState *opp; /* Device timer is part of. */
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2021-09-18 05:26:53 +02:00
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/*
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* The QEMU_CLOCK_VIRTUAL time (in ns) corresponding to the last
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* current_count written or read, only defined if qemu_timer_active.
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*/
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2018-02-28 21:32:40 +01:00
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uint64_t origin_time;
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} OpenPICTimer;
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typedef struct OpenPICMSI {
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uint32_t msir; /* Shared Message Signaled Interrupt Register */
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} OpenPICMSI;
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typedef struct IRQDest {
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int32_t ctpr; /* CPU current task priority */
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IRQQueue raised;
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IRQQueue servicing;
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qemu_irq *irqs;
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/* Count of IRQ sources asserting on non-INT outputs */
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uint32_t outputs_active[OPENPIC_OUTPUT_NB];
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} IRQDest;
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#define TYPE_OPENPIC "openpic"
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2020-09-16 20:25:19 +02:00
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OBJECT_DECLARE_SIMPLE_TYPE(OpenPICState, OPENPIC)
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2018-02-28 21:32:40 +01:00
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2020-09-03 22:43:22 +02:00
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struct OpenPICState {
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2018-02-28 21:32:40 +01:00
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mem;
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/* Behavior control */
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FslMpicInfo *fsl;
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uint32_t model;
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uint32_t flags;
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uint32_t nb_irqs;
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uint32_t vid;
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uint32_t vir; /* Vendor identification register */
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uint32_t vector_mask;
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uint32_t tfrr_reset;
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uint32_t ivpr_reset;
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uint32_t idr_reset;
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uint32_t brr1;
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uint32_t mpic_mode_mask;
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/* Sub-regions */
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MemoryRegion sub_io_mem[6];
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/* Global registers */
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uint32_t frr; /* Feature reporting register */
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uint32_t gcr; /* Global configuration register */
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uint32_t pir; /* Processor initialization register */
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uint32_t spve; /* Spurious vector register */
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uint32_t tfrr; /* Timer frequency reporting register */
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/* Source registers */
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IRQSource src[OPENPIC_MAX_IRQ];
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/* Local registers per output pin */
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IRQDest dst[MAX_CPU];
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uint32_t nb_cpus;
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/* Timer registers */
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OpenPICTimer timers[OPENPIC_MAX_TMR];
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uint32_t max_tmr;
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/* Shared MSI registers */
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OpenPICMSI msi[MAX_MSI];
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uint32_t max_irq;
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uint32_t irq_ipi0;
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uint32_t irq_tim0;
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uint32_t irq_msi;
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2020-09-03 22:43:22 +02:00
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};
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2018-02-28 21:32:40 +01:00
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2016-06-29 13:47:03 +02:00
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#endif /* OPENPIC_H */
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