2004-06-03 20:46:20 +02:00
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/*
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2007-10-29 00:42:18 +01:00
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* QEMU PowerMac CUDA device support
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2007-09-16 23:08:06 +02:00
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*
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2007-10-29 00:42:18 +01:00
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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2007-09-16 23:08:06 +02:00
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*
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2004-06-03 20:46:20 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2013-02-04 15:40:22 +01:00
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/input/adb.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/timer.h"
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2012-12-17 18:20:04 +01:00
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#include "sysemu/sysemu.h"
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2004-06-03 20:46:20 +02:00
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2005-07-07 23:45:18 +02:00
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/* XXX: implement all timer modes */
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2008-12-24 10:38:16 +01:00
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/* debug CUDA */
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2004-06-21 18:47:13 +02:00
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//#define DEBUG_CUDA
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2008-12-24 10:38:16 +01:00
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/* debug CUDA packets */
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2004-06-21 18:47:13 +02:00
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//#define DEBUG_CUDA_PACKET
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2008-12-24 10:38:16 +01:00
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#ifdef DEBUG_CUDA
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2009-05-13 19:53:17 +02:00
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#define CUDA_DPRINTF(fmt, ...) \
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do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
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2008-12-24 10:38:16 +01:00
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#else
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2009-05-13 19:53:17 +02:00
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#define CUDA_DPRINTF(fmt, ...)
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2008-12-24 10:38:16 +01:00
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#endif
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2004-06-03 20:46:20 +02:00
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/* Bits in B data register: all active low */
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#define TREQ 0x08 /* Transfer request (input) */
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#define TACK 0x10 /* Transfer acknowledge (output) */
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#define TIP 0x20 /* Transfer in progress (output) */
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/* Bits in ACR */
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#define SR_CTRL 0x1c /* Shift register control bits */
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#define SR_EXT 0x0c /* Shift on external clock */
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#define SR_OUT 0x10 /* Shift out if 1 */
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/* Bits in IFR and IER */
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#define IER_SET 0x80 /* set bits in IER */
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#define IER_CLR 0 /* clear bits in IER */
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#define SR_INT 0x04 /* Shift register full/empty */
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2015-11-11 23:49:46 +01:00
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#define SR_DATA_INT 0x08
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#define SR_CLOCK_INT 0x10
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2004-06-03 20:46:20 +02:00
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#define T1_INT 0x40 /* Timer 1 interrupt */
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2005-07-07 23:45:18 +02:00
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#define T2_INT 0x20 /* Timer 2 interrupt */
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2004-06-03 20:46:20 +02:00
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/* Bits in ACR */
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#define T1MODE 0xc0 /* Timer 1 mode */
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#define T1MODE_CONT 0x40 /* continuous interrupts */
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/* commands (1st byte) */
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#define ADB_PACKET 0
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#define CUDA_PACKET 1
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#define ERROR_PACKET 2
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#define TIMER_PACKET 3
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#define POWER_PACKET 4
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#define MACIIC_PACKET 5
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#define PMU_PACKET 6
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/* CUDA commands (2nd byte) */
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#define CUDA_WARM_START 0x0
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#define CUDA_AUTOPOLL 0x1
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#define CUDA_GET_6805_ADDR 0x2
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#define CUDA_GET_TIME 0x3
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#define CUDA_GET_PRAM 0x7
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#define CUDA_SET_6805_ADDR 0x8
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#define CUDA_SET_TIME 0x9
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#define CUDA_POWERDOWN 0xa
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#define CUDA_POWERUP_TIME 0xb
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#define CUDA_SET_PRAM 0xc
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#define CUDA_MS_RESET 0xd
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#define CUDA_SEND_DFAC 0xe
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#define CUDA_BATTERY_SWAP_SENSE 0x10
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#define CUDA_RESET_SYSTEM 0x11
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#define CUDA_SET_IPL 0x12
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#define CUDA_FILE_SERVER_FLAG 0x13
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#define CUDA_SET_AUTO_RATE 0x14
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#define CUDA_GET_AUTO_RATE 0x16
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#define CUDA_SET_DEVICE_LIST 0x19
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#define CUDA_GET_DEVICE_LIST 0x1a
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#define CUDA_SET_ONE_SECOND_MODE 0x1b
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#define CUDA_SET_POWER_MESSAGES 0x21
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#define CUDA_GET_SET_IIC 0x22
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#define CUDA_WAKEUP 0x23
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#define CUDA_TIMER_TICKLE 0x24
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#define CUDA_COMBINED_FORMAT_IIC 0x25
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#define CUDA_TIMER_FREQ (4700000 / 6)
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2004-06-22 00:46:10 +02:00
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#define CUDA_ADB_POLL_FREQ 50
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2004-06-03 20:46:20 +02:00
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2005-02-09 01:07:08 +01:00
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/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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#define RTC_OFFSET 2082844800
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2015-11-11 23:49:47 +01:00
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/* CUDA registers */
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#define CUDA_REG_B 0x00
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#define CUDA_REG_A 0x01
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#define CUDA_REG_DIRB 0x02
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#define CUDA_REG_DIRA 0x03
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#define CUDA_REG_T1CL 0x04
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#define CUDA_REG_T1CH 0x05
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#define CUDA_REG_T1LL 0x06
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#define CUDA_REG_T1LH 0x07
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#define CUDA_REG_T2CL 0x08
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#define CUDA_REG_T2CH 0x09
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#define CUDA_REG_SR 0x0a
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#define CUDA_REG_ACR 0x0b
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#define CUDA_REG_PCR 0x0c
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#define CUDA_REG_IFR 0x0d
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#define CUDA_REG_IER 0x0e
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#define CUDA_REG_ANH 0x0f
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2004-06-03 20:46:20 +02:00
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static void cuda_update(CUDAState *s);
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2007-09-16 23:08:06 +02:00
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static void cuda_receive_packet_from_host(CUDAState *s,
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2004-06-03 20:46:20 +02:00
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const uint8_t *data, int len);
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2007-09-16 23:08:06 +02:00
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static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
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2004-06-21 18:47:13 +02:00
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int64_t current_time);
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2004-06-03 20:46:20 +02:00
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static void cuda_update_irq(CUDAState *s)
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{
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2004-06-21 18:47:13 +02:00
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if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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2007-04-07 20:14:41 +02:00
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qemu_irq_raise(s->irq);
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2004-06-03 20:46:20 +02:00
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} else {
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2007-04-07 20:14:41 +02:00
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qemu_irq_lower(s->irq);
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2004-06-03 20:46:20 +02:00
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}
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}
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2015-11-11 23:49:48 +01:00
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static uint64_t get_tb(uint64_t time, uint64_t freq)
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2014-07-13 22:31:53 +02:00
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{
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2015-11-11 23:49:48 +01:00
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return muldiv64(time, freq, get_ticks_per_sec());
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2014-07-13 22:31:53 +02:00
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}
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2004-06-03 20:46:20 +02:00
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static unsigned int get_counter(CUDATimer *s)
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{
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int64_t d;
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unsigned int counter;
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2014-07-13 22:31:53 +02:00
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uint64_t tb_diff;
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2015-11-11 23:49:48 +01:00
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uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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2014-07-13 22:31:53 +02:00
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/* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */
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2015-11-11 23:49:48 +01:00
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tb_diff = get_tb(current_time, s->frequency) - s->load_time;
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2014-07-13 22:31:53 +02:00
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d = (tb_diff * 0xBF401675E5DULL) / (s->frequency << 24);
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2004-06-03 20:46:20 +02:00
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2005-07-07 23:45:18 +02:00
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if (s->index == 0) {
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (s->counter_value + 1)) {
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counter = (s->counter_value - d) & 0xffff;
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} else {
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counter = (d - (s->counter_value + 1)) % (s->latch + 2);
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2007-09-16 23:08:06 +02:00
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counter = (s->latch - counter) & 0xffff;
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2005-07-07 23:45:18 +02:00
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}
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2004-06-03 20:46:20 +02:00
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} else {
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2005-07-07 23:45:18 +02:00
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counter = (s->counter_value - d) & 0xffff;
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2004-06-03 20:46:20 +02:00
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}
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return counter;
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}
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2004-06-21 18:47:13 +02:00
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static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
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2004-06-03 20:46:20 +02:00
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{
|
2008-12-24 10:38:16 +01:00
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CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val);
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2015-11-11 23:49:48 +01:00
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ti->load_time = get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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s->frequency);
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2004-06-21 18:47:13 +02:00
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ti->counter_value = val;
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cuda_timer_update(s, ti, ti->load_time);
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2004-06-03 20:46:20 +02:00
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}
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static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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{
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2005-07-07 23:45:18 +02:00
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int64_t d, next_time;
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unsigned int counter;
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2004-06-03 20:46:20 +02:00
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/* current counter value */
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2007-09-16 23:08:06 +02:00
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d = muldiv64(current_time - s->load_time,
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2009-09-10 03:04:26 +02:00
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CUDA_TIMER_FREQ, get_ticks_per_sec());
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2005-07-07 23:45:18 +02:00
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/* the timer goes down from latch to -1 (period of latch + 2) */
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if (d <= (s->counter_value + 1)) {
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counter = (s->counter_value - d) & 0xffff;
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} else {
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counter = (d - (s->counter_value + 1)) % (s->latch + 2);
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2007-09-16 23:08:06 +02:00
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counter = (s->latch - counter) & 0xffff;
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2005-07-07 23:45:18 +02:00
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}
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2007-09-17 10:09:54 +02:00
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2005-07-07 23:45:18 +02:00
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/* Note: we consider the irq is raised on 0 */
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if (counter == 0xffff) {
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next_time = d + s->latch + 1;
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} else if (counter == 0) {
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next_time = d + s->latch + 2;
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} else {
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next_time = d + counter;
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2004-06-03 20:46:20 +02:00
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}
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2008-12-24 10:38:16 +01:00
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CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
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s->latch, d, next_time - d);
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2009-09-10 03:04:26 +02:00
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next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) +
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2004-06-03 20:46:20 +02:00
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s->load_time;
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if (next_time <= current_time)
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next_time = current_time + 1;
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return next_time;
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}
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2007-09-16 23:08:06 +02:00
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static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
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2004-06-21 18:47:13 +02:00
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int64_t current_time)
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{
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if (!ti->timer)
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return;
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if ((s->acr & T1MODE) != T1MODE_CONT) {
|
2013-08-21 17:03:08 +02:00
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timer_del(ti->timer);
|
2004-06-21 18:47:13 +02:00
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} else {
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ti->next_irq_time = get_next_irq_time(ti, current_time);
|
2013-08-21 17:03:08 +02:00
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timer_mod(ti->timer, ti->next_irq_time);
|
2004-06-21 18:47:13 +02:00
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}
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}
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2004-06-03 20:46:20 +02:00
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static void cuda_timer1(void *opaque)
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{
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CUDAState *s = opaque;
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CUDATimer *ti = &s->timers[0];
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|
2004-06-21 18:47:13 +02:00
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cuda_timer_update(s, ti, ti->next_irq_time);
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2004-06-03 20:46:20 +02:00
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s->ifr |= T1_INT;
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cuda_update_irq(s);
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}
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|
2012-10-23 12:30:10 +02:00
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static uint32_t cuda_readb(void *opaque, hwaddr addr)
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2004-06-03 20:46:20 +02:00
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{
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CUDAState *s = opaque;
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uint32_t val;
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addr = (addr >> 9) & 0xf;
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switch(addr) {
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2015-11-11 23:49:47 +01:00
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case CUDA_REG_B:
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2004-06-03 20:46:20 +02:00
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val = s->b;
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break;
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2015-11-11 23:49:47 +01:00
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case CUDA_REG_A:
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2004-06-03 20:46:20 +02:00
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val = s->a;
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break;
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2015-11-11 23:49:47 +01:00
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case CUDA_REG_DIRB:
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2004-06-03 20:46:20 +02:00
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val = s->dirb;
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break;
|
2015-11-11 23:49:47 +01:00
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case CUDA_REG_DIRA:
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2004-06-03 20:46:20 +02:00
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val = s->dira;
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break;
|
2015-11-11 23:49:47 +01:00
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case CUDA_REG_T1CL:
|
2004-06-03 20:46:20 +02:00
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val = get_counter(&s->timers[0]) & 0xff;
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s->ifr &= ~T1_INT;
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|
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cuda_update_irq(s);
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break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T1CH:
|
2004-06-03 20:46:20 +02:00
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val = get_counter(&s->timers[0]) >> 8;
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cuda_update_irq(s);
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|
break;
|
2015-11-11 23:49:47 +01:00
|
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case CUDA_REG_T1LL:
|
2004-06-03 20:46:20 +02:00
|
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val = s->timers[0].latch & 0xff;
|
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|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T1LH:
|
2005-07-07 23:45:18 +02:00
|
|
|
/* XXX: check this */
|
2004-06-03 20:46:20 +02:00
|
|
|
val = (s->timers[0].latch >> 8) & 0xff;
|
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|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T2CL:
|
2004-06-03 20:46:20 +02:00
|
|
|
val = get_counter(&s->timers[1]) & 0xff;
|
2005-07-07 23:45:18 +02:00
|
|
|
s->ifr &= ~T2_INT;
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T2CH:
|
2004-06-03 20:46:20 +02:00
|
|
|
val = get_counter(&s->timers[1]) >> 8;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_SR:
|
2004-06-21 18:47:13 +02:00
|
|
|
val = s->sr;
|
2015-11-11 23:49:46 +01:00
|
|
|
s->ifr &= ~(SR_INT | SR_CLOCK_INT | SR_DATA_INT);
|
2004-06-21 18:47:13 +02:00
|
|
|
cuda_update_irq(s);
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_ACR:
|
2004-06-03 20:46:20 +02:00
|
|
|
val = s->acr;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_PCR:
|
2004-06-03 20:46:20 +02:00
|
|
|
val = s->pcr;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_IFR:
|
2004-06-03 20:46:20 +02:00
|
|
|
val = s->ifr;
|
2015-11-11 23:49:47 +01:00
|
|
|
if (s->ifr & s->ier) {
|
2005-07-23 16:01:47 +02:00
|
|
|
val |= 0x80;
|
2015-11-11 23:49:47 +01:00
|
|
|
}
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_IER:
|
2005-07-23 16:01:47 +02:00
|
|
|
val = s->ier | 0x80;
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
|
|
|
default:
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_ANH:
|
2004-06-03 20:46:20 +02:00
|
|
|
val = s->anh;
|
|
|
|
break;
|
|
|
|
}
|
2015-11-11 23:49:47 +01:00
|
|
|
if (addr != CUDA_REG_IFR || val != 0) {
|
2008-12-24 10:38:16 +01:00
|
|
|
CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val);
|
2010-04-18 10:45:03 +02:00
|
|
|
}
|
|
|
|
|
2004-06-03 20:46:20 +02:00
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void cuda_writeb(void *opaque, hwaddr addr, uint32_t val)
|
2004-06-03 20:46:20 +02:00
|
|
|
{
|
|
|
|
CUDAState *s = opaque;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2004-06-03 20:46:20 +02:00
|
|
|
addr = (addr >> 9) & 0xf;
|
2008-12-24 10:38:16 +01:00
|
|
|
CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val);
|
2004-06-03 20:46:20 +02:00
|
|
|
|
|
|
|
switch(addr) {
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_B:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->b = val;
|
|
|
|
cuda_update(s);
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_A:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->a = val;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_DIRB:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->dirb = val;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_DIRA:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->dira = val;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T1CL:
|
2005-07-07 23:45:18 +02:00
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
|
2013-08-21 17:03:08 +02:00
|
|
|
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T1CH:
|
2005-07-07 23:45:18 +02:00
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
|
|
|
|
s->ifr &= ~T1_INT;
|
|
|
|
set_counter(s, &s->timers[0], s->timers[0].latch);
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T1LL:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
|
2013-08-21 17:03:08 +02:00
|
|
|
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T1LH:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
|
2005-07-07 23:45:18 +02:00
|
|
|
s->ifr &= ~T1_INT;
|
2013-08-21 17:03:08 +02:00
|
|
|
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T2CL:
|
2005-07-07 23:45:18 +02:00
|
|
|
s->timers[1].latch = val;
|
2004-06-21 18:47:13 +02:00
|
|
|
set_counter(s, &s->timers[1], val);
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_T2CH:
|
2005-07-07 23:45:18 +02:00
|
|
|
set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_SR:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->sr = val;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_ACR:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->acr = val;
|
2013-08-21 17:03:08 +02:00
|
|
|
cuda_timer_update(s, &s->timers[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
2004-06-03 20:46:20 +02:00
|
|
|
cuda_update(s);
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_PCR:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->pcr = val;
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_IFR:
|
2004-06-03 20:46:20 +02:00
|
|
|
/* reset bits */
|
|
|
|
s->ifr &= ~val;
|
|
|
|
cuda_update_irq(s);
|
|
|
|
break;
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_IER:
|
2004-06-03 20:46:20 +02:00
|
|
|
if (val & IER_SET) {
|
|
|
|
/* set bits */
|
|
|
|
s->ier |= val & 0x7f;
|
|
|
|
} else {
|
|
|
|
/* reset bits */
|
|
|
|
s->ier &= ~val;
|
|
|
|
}
|
|
|
|
cuda_update_irq(s);
|
|
|
|
break;
|
|
|
|
default:
|
2015-11-11 23:49:47 +01:00
|
|
|
case CUDA_REG_ANH:
|
2004-06-03 20:46:20 +02:00
|
|
|
s->anh = val;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NOTE: TIP and TREQ are negated */
|
|
|
|
static void cuda_update(CUDAState *s)
|
|
|
|
{
|
2004-06-21 18:47:13 +02:00
|
|
|
int packet_received, len;
|
|
|
|
|
|
|
|
packet_received = 0;
|
|
|
|
if (!(s->b & TIP)) {
|
|
|
|
/* transfer requested from host */
|
2004-06-03 20:46:20 +02:00
|
|
|
|
2004-06-21 18:47:13 +02:00
|
|
|
if (s->acr & SR_OUT) {
|
|
|
|
/* data output */
|
|
|
|
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
|
|
|
if (s->data_out_index < sizeof(s->data_out)) {
|
2008-12-24 10:38:16 +01:00
|
|
|
CUDA_DPRINTF("send: %02x\n", s->sr);
|
2004-06-21 18:47:13 +02:00
|
|
|
s->data_out[s->data_out_index++] = s->sr;
|
|
|
|
s->ifr |= SR_INT;
|
|
|
|
cuda_update_irq(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (s->data_in_index < s->data_in_size) {
|
|
|
|
/* data input */
|
|
|
|
if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
|
|
|
s->sr = s->data_in[s->data_in_index++];
|
2008-12-24 10:38:16 +01:00
|
|
|
CUDA_DPRINTF("recv: %02x\n", s->sr);
|
2004-06-21 18:47:13 +02:00
|
|
|
/* indicate end of transfer */
|
|
|
|
if (s->data_in_index >= s->data_in_size) {
|
|
|
|
s->b = (s->b | TREQ);
|
|
|
|
}
|
|
|
|
s->ifr |= SR_INT;
|
|
|
|
cuda_update_irq(s);
|
|
|
|
}
|
2004-06-03 20:46:20 +02:00
|
|
|
}
|
2004-06-21 18:47:13 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* no transfer requested: handle sync case */
|
|
|
|
if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
|
|
|
/* update TREQ state each time TACK change state */
|
|
|
|
if (s->b & TACK)
|
|
|
|
s->b = (s->b | TREQ);
|
|
|
|
else
|
|
|
|
s->b = (s->b & ~TREQ);
|
2004-06-03 20:46:20 +02:00
|
|
|
s->ifr |= SR_INT;
|
|
|
|
cuda_update_irq(s);
|
2004-06-21 18:47:13 +02:00
|
|
|
} else {
|
|
|
|
if (!(s->last_b & TIP)) {
|
2007-06-03 15:35:16 +02:00
|
|
|
/* handle end of host to cuda transfer */
|
2004-06-21 18:47:13 +02:00
|
|
|
packet_received = (s->data_out_index > 0);
|
2007-06-03 15:35:16 +02:00
|
|
|
/* always an IRQ at the end of transfer */
|
2004-06-21 18:47:13 +02:00
|
|
|
s->ifr |= SR_INT;
|
|
|
|
cuda_update_irq(s);
|
|
|
|
}
|
|
|
|
/* signal if there is data to read */
|
|
|
|
if (s->data_in_index < s->data_in_size) {
|
|
|
|
s->b = (s->b & ~TREQ);
|
|
|
|
}
|
2004-06-03 20:46:20 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
s->last_acr = s->acr;
|
|
|
|
s->last_b = s->b;
|
2004-06-21 18:47:13 +02:00
|
|
|
|
|
|
|
/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
|
|
|
recursively */
|
|
|
|
if (packet_received) {
|
|
|
|
len = s->data_out_index;
|
|
|
|
s->data_out_index = 0;
|
|
|
|
cuda_receive_packet_from_host(s, s->data_out, len);
|
|
|
|
}
|
2004-06-03 20:46:20 +02:00
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
static void cuda_send_packet_to_host(CUDAState *s,
|
2004-06-03 20:46:20 +02:00
|
|
|
const uint8_t *data, int len)
|
|
|
|
{
|
2004-06-21 18:47:13 +02:00
|
|
|
#ifdef DEBUG_CUDA_PACKET
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
printf("cuda_send_packet_to_host:\n");
|
|
|
|
for(i = 0; i < len; i++)
|
|
|
|
printf(" %02x", data[i]);
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
#endif
|
2004-06-03 20:46:20 +02:00
|
|
|
memcpy(s->data_in, data, len);
|
|
|
|
s->data_in_size = len;
|
|
|
|
s->data_in_index = 0;
|
|
|
|
cuda_update(s);
|
|
|
|
s->ifr |= SR_INT;
|
|
|
|
cuda_update_irq(s);
|
|
|
|
}
|
|
|
|
|
2004-07-06 22:57:47 +02:00
|
|
|
static void cuda_adb_poll(void *opaque)
|
2004-06-22 00:46:10 +02:00
|
|
|
{
|
|
|
|
CUDAState *s = opaque;
|
|
|
|
uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
|
|
|
int olen;
|
|
|
|
|
2013-01-24 00:04:05 +01:00
|
|
|
olen = adb_poll(&s->adb_bus, obuf + 2);
|
2004-06-22 00:46:10 +02:00
|
|
|
if (olen > 0) {
|
|
|
|
obuf[0] = ADB_PACKET;
|
|
|
|
obuf[1] = 0x40; /* polled data */
|
|
|
|
cuda_send_packet_to_host(s, obuf, olen + 2);
|
|
|
|
}
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_mod(s->adb_poll_timer,
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
2009-09-10 03:04:26 +02:00
|
|
|
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
|
2004-06-22 00:46:10 +02:00
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
static void cuda_receive_packet(CUDAState *s,
|
2004-06-03 20:46:20 +02:00
|
|
|
const uint8_t *data, int len)
|
|
|
|
{
|
2015-11-11 23:49:43 +01:00
|
|
|
uint8_t obuf[16] = { CUDA_PACKET, 0, data[0] };
|
2009-01-15 19:57:15 +01:00
|
|
|
int autopoll;
|
|
|
|
uint32_t ti;
|
2004-06-03 20:46:20 +02:00
|
|
|
|
|
|
|
switch(data[0]) {
|
|
|
|
case CUDA_AUTOPOLL:
|
2004-06-22 00:46:10 +02:00
|
|
|
autopoll = (data[1] != 0);
|
|
|
|
if (autopoll != s->autopoll) {
|
|
|
|
s->autopoll = autopoll;
|
|
|
|
if (autopoll) {
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_mod(s->adb_poll_timer,
|
|
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
2009-09-10 03:04:26 +02:00
|
|
|
(get_ticks_per_sec() / CUDA_ADB_POLL_FREQ));
|
2004-06-22 00:46:10 +02:00
|
|
|
} else {
|
2013-08-21 17:03:08 +02:00
|
|
|
timer_del(s->adb_poll_timer);
|
2004-06-22 00:46:10 +02:00
|
|
|
}
|
|
|
|
}
|
2015-11-11 23:49:43 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2015-11-11 23:49:44 +01:00
|
|
|
case CUDA_GET_6805_ADDR:
|
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
|
|
|
break;
|
2005-04-23 20:16:54 +02:00
|
|
|
case CUDA_SET_TIME:
|
2009-01-15 19:57:15 +01:00
|
|
|
ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4];
|
2013-08-21 17:03:08 +02:00
|
|
|
s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
|
2009-01-15 19:57:15 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
|
|
|
break;
|
|
|
|
case CUDA_GET_TIME:
|
2013-08-21 17:03:08 +02:00
|
|
|
ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec());
|
2004-06-03 20:46:20 +02:00
|
|
|
obuf[3] = ti >> 24;
|
|
|
|
obuf[4] = ti >> 16;
|
|
|
|
obuf[5] = ti >> 8;
|
|
|
|
obuf[6] = ti;
|
|
|
|
cuda_send_packet_to_host(s, obuf, 7);
|
|
|
|
break;
|
|
|
|
case CUDA_FILE_SERVER_FLAG:
|
|
|
|
case CUDA_SET_DEVICE_LIST:
|
|
|
|
case CUDA_SET_AUTO_RATE:
|
|
|
|
case CUDA_SET_POWER_MESSAGES:
|
2015-11-11 23:49:43 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
2005-02-09 01:07:08 +01:00
|
|
|
case CUDA_POWERDOWN:
|
2015-11-11 23:49:43 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
2009-01-15 19:57:25 +01:00
|
|
|
qemu_system_shutdown_request();
|
|
|
|
break;
|
2007-09-19 06:46:57 +02:00
|
|
|
case CUDA_RESET_SYSTEM:
|
2015-11-11 23:49:43 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
2007-09-19 06:46:57 +02:00
|
|
|
qemu_system_reset_request();
|
|
|
|
break;
|
2015-11-11 23:49:45 +01:00
|
|
|
case CUDA_COMBINED_FORMAT_IIC:
|
|
|
|
obuf[0] = ERROR_PACKET;
|
|
|
|
obuf[1] = 0x5;
|
|
|
|
obuf[2] = CUDA_PACKET;
|
|
|
|
obuf[3] = data[0];
|
|
|
|
cuda_send_packet_to_host(s, obuf, 4);
|
|
|
|
break;
|
|
|
|
case CUDA_GET_SET_IIC:
|
|
|
|
if (len == 4) {
|
|
|
|
cuda_send_packet_to_host(s, obuf, 3);
|
|
|
|
} else {
|
|
|
|
obuf[0] = ERROR_PACKET;
|
|
|
|
obuf[1] = 0x2;
|
|
|
|
obuf[2] = CUDA_PACKET;
|
|
|
|
obuf[3] = data[0];
|
|
|
|
cuda_send_packet_to_host(s, obuf, 4);
|
|
|
|
}
|
|
|
|
break;
|
2004-06-03 20:46:20 +02:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-16 23:08:06 +02:00
|
|
|
static void cuda_receive_packet_from_host(CUDAState *s,
|
2004-06-03 20:46:20 +02:00
|
|
|
const uint8_t *data, int len)
|
|
|
|
{
|
2004-06-21 18:47:13 +02:00
|
|
|
#ifdef DEBUG_CUDA_PACKET
|
|
|
|
{
|
|
|
|
int i;
|
2005-06-05 17:24:23 +02:00
|
|
|
printf("cuda_receive_packet_from_host:\n");
|
2004-06-21 18:47:13 +02:00
|
|
|
for(i = 0; i < len; i++)
|
|
|
|
printf(" %02x", data[i]);
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
#endif
|
2004-06-03 20:46:20 +02:00
|
|
|
switch(data[0]) {
|
|
|
|
case ADB_PACKET:
|
2004-06-22 00:46:10 +02:00
|
|
|
{
|
2015-11-11 23:49:42 +01:00
|
|
|
uint8_t obuf[ADB_MAX_OUT_LEN + 3];
|
2004-06-22 00:46:10 +02:00
|
|
|
int olen;
|
2013-01-24 00:04:05 +01:00
|
|
|
olen = adb_request(&s->adb_bus, obuf + 2, data + 1, len - 1);
|
2004-07-12 22:16:00 +02:00
|
|
|
if (olen > 0) {
|
2004-06-22 00:46:10 +02:00
|
|
|
obuf[0] = ADB_PACKET;
|
|
|
|
obuf[1] = 0x00;
|
2015-11-11 23:49:42 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, olen + 2);
|
2004-06-22 00:46:10 +02:00
|
|
|
} else {
|
2004-07-12 22:16:00 +02:00
|
|
|
/* error */
|
2004-06-22 00:46:10 +02:00
|
|
|
obuf[0] = ADB_PACKET;
|
2004-07-12 22:16:00 +02:00
|
|
|
obuf[1] = -olen;
|
2015-11-11 23:49:42 +01:00
|
|
|
obuf[2] = data[1];
|
2004-07-12 22:16:00 +02:00
|
|
|
olen = 0;
|
2015-11-11 23:49:42 +01:00
|
|
|
cuda_send_packet_to_host(s, obuf, olen + 3);
|
2004-06-22 00:46:10 +02:00
|
|
|
}
|
|
|
|
}
|
2004-06-03 20:46:20 +02:00
|
|
|
break;
|
|
|
|
case CUDA_PACKET:
|
|
|
|
cuda_receive_packet(s, data + 1, len - 1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void cuda_writew (void *opaque, hwaddr addr, uint32_t value)
|
2004-06-03 20:46:20 +02:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void cuda_writel (void *opaque, hwaddr addr, uint32_t value)
|
2004-06-03 20:46:20 +02:00
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t cuda_readw (void *opaque, hwaddr addr)
|
2004-06-03 20:46:20 +02:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t cuda_readl (void *opaque, hwaddr addr)
|
2004-06-03 20:46:20 +02:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-02-05 11:19:07 +01:00
|
|
|
static const MemoryRegionOps cuda_ops = {
|
2011-09-08 18:51:17 +02:00
|
|
|
.old_mmio = {
|
|
|
|
.write = {
|
|
|
|
cuda_writeb,
|
|
|
|
cuda_writew,
|
|
|
|
cuda_writel,
|
|
|
|
},
|
|
|
|
.read = {
|
|
|
|
cuda_readb,
|
|
|
|
cuda_readw,
|
|
|
|
cuda_readl,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2004-06-03 20:46:20 +02:00
|
|
|
};
|
|
|
|
|
2010-12-02 13:53:24 +01:00
|
|
|
static bool cuda_timer_exist(void *opaque, int version_id)
|
2008-12-30 20:01:19 +01:00
|
|
|
{
|
2010-12-02 13:53:24 +01:00
|
|
|
CUDATimer *s = opaque;
|
2008-12-30 20:01:19 +01:00
|
|
|
|
2010-12-02 13:53:24 +01:00
|
|
|
return s->timer != NULL;
|
2008-12-30 20:01:19 +01:00
|
|
|
}
|
|
|
|
|
2010-12-02 13:53:24 +01:00
|
|
|
static const VMStateDescription vmstate_cuda_timer = {
|
|
|
|
.name = "cuda_timer",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
2014-04-16 16:01:33 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-02 13:53:24 +01:00
|
|
|
VMSTATE_UINT16(latch, CUDATimer),
|
|
|
|
VMSTATE_UINT16(counter_value, CUDATimer),
|
|
|
|
VMSTATE_INT64(load_time, CUDATimer),
|
|
|
|
VMSTATE_INT64(next_irq_time, CUDATimer),
|
2015-01-08 10:18:59 +01:00
|
|
|
VMSTATE_TIMER_PTR_TEST(timer, CUDATimer, cuda_timer_exist),
|
2010-12-02 13:53:24 +01:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-12-30 20:01:19 +01:00
|
|
|
|
2010-12-02 13:53:24 +01:00
|
|
|
static const VMStateDescription vmstate_cuda = {
|
|
|
|
.name = "cuda",
|
2015-02-09 23:40:46 +01:00
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 2,
|
2014-04-16 16:01:33 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-02 13:53:24 +01:00
|
|
|
VMSTATE_UINT8(a, CUDAState),
|
|
|
|
VMSTATE_UINT8(b, CUDAState),
|
|
|
|
VMSTATE_UINT8(dira, CUDAState),
|
|
|
|
VMSTATE_UINT8(dirb, CUDAState),
|
|
|
|
VMSTATE_UINT8(sr, CUDAState),
|
|
|
|
VMSTATE_UINT8(acr, CUDAState),
|
|
|
|
VMSTATE_UINT8(pcr, CUDAState),
|
|
|
|
VMSTATE_UINT8(ifr, CUDAState),
|
|
|
|
VMSTATE_UINT8(ier, CUDAState),
|
|
|
|
VMSTATE_UINT8(anh, CUDAState),
|
|
|
|
VMSTATE_INT32(data_in_size, CUDAState),
|
|
|
|
VMSTATE_INT32(data_in_index, CUDAState),
|
|
|
|
VMSTATE_INT32(data_out_index, CUDAState),
|
|
|
|
VMSTATE_UINT8(autopoll, CUDAState),
|
|
|
|
VMSTATE_BUFFER(data_in, CUDAState),
|
|
|
|
VMSTATE_BUFFER(data_out, CUDAState),
|
|
|
|
VMSTATE_UINT32(tick_offset, CUDAState),
|
|
|
|
VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1,
|
|
|
|
vmstate_cuda_timer, CUDATimer),
|
2015-02-09 23:40:46 +01:00
|
|
|
VMSTATE_TIMER_PTR(adb_poll_timer, CUDAState),
|
2010-12-02 13:53:24 +01:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-12-30 20:01:19 +01:00
|
|
|
|
2013-01-24 00:04:02 +01:00
|
|
|
static void cuda_reset(DeviceState *dev)
|
2008-12-28 19:27:10 +01:00
|
|
|
{
|
2013-01-24 00:04:02 +01:00
|
|
|
CUDAState *s = CUDA(dev);
|
2008-12-28 19:27:10 +01:00
|
|
|
|
|
|
|
s->b = 0;
|
|
|
|
s->a = 0;
|
|
|
|
s->dirb = 0;
|
|
|
|
s->dira = 0;
|
|
|
|
s->sr = 0;
|
|
|
|
s->acr = 0;
|
|
|
|
s->pcr = 0;
|
|
|
|
s->ifr = 0;
|
|
|
|
s->ier = 0;
|
|
|
|
// s->ier = T1_INT | SR_INT;
|
|
|
|
s->anh = 0;
|
|
|
|
s->data_in_size = 0;
|
|
|
|
s->data_in_index = 0;
|
|
|
|
s->data_out_index = 0;
|
|
|
|
s->autopoll = 0;
|
|
|
|
|
|
|
|
s->timers[0].latch = 0xffff;
|
|
|
|
set_counter(s, &s->timers[0], 0xffff);
|
|
|
|
|
|
|
|
s->timers[1].latch = 0;
|
|
|
|
set_counter(s, &s->timers[1], 0xffff);
|
|
|
|
}
|
|
|
|
|
2013-01-24 00:04:02 +01:00
|
|
|
static void cuda_realizefn(DeviceState *dev, Error **errp)
|
2004-06-03 20:46:20 +02:00
|
|
|
{
|
2013-01-24 00:04:02 +01:00
|
|
|
CUDAState *s = CUDA(dev);
|
2009-01-15 19:57:15 +01:00
|
|
|
struct tm tm;
|
2004-06-21 18:47:13 +02:00
|
|
|
|
2013-08-21 17:03:08 +02:00
|
|
|
s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_timer1, s);
|
2014-07-13 22:31:53 +02:00
|
|
|
s->timers[0].frequency = s->frequency;
|
|
|
|
s->timers[1].frequency = s->frequency;
|
2005-07-07 23:45:18 +02:00
|
|
|
|
2009-01-18 13:16:26 +01:00
|
|
|
qemu_get_timedate(&tm, 0);
|
|
|
|
s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
|
2009-01-15 19:57:15 +01:00
|
|
|
|
2013-08-21 17:03:08 +02:00
|
|
|
s->adb_poll_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cuda_adb_poll, s);
|
2013-01-24 00:04:02 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static void cuda_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *d = SYS_BUS_DEVICE(obj);
|
|
|
|
CUDAState *s = CUDA(obj);
|
|
|
|
int i;
|
|
|
|
|
2015-10-01 10:59:51 +02:00
|
|
|
memory_region_init_io(&s->mem, obj, &cuda_ops, s, "cuda", 0x2000);
|
2013-01-24 00:04:02 +01:00
|
|
|
sysbus_init_mmio(d, &s->mem);
|
|
|
|
sysbus_init_irq(d, &s->irq);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
|
|
|
|
s->timers[i].index = i;
|
|
|
|
}
|
2013-01-24 00:04:03 +01:00
|
|
|
|
2013-08-24 00:02:27 +02:00
|
|
|
qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
|
|
|
|
DEVICE(obj), "adb.0");
|
2013-01-24 00:04:02 +01:00
|
|
|
}
|
|
|
|
|
2014-07-13 22:31:53 +02:00
|
|
|
static Property cuda_properties[] = {
|
|
|
|
DEFINE_PROP_UINT64("frequency", CUDAState, frequency, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST()
|
|
|
|
};
|
|
|
|
|
2013-01-24 00:04:02 +01:00
|
|
|
static void cuda_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
2011-09-08 18:51:17 +02:00
|
|
|
|
2013-01-24 00:04:02 +01:00
|
|
|
dc->realize = cuda_realizefn;
|
|
|
|
dc->reset = cuda_reset;
|
|
|
|
dc->vmsd = &vmstate_cuda;
|
2014-07-13 22:31:53 +02:00
|
|
|
dc->props = cuda_properties;
|
2015-09-26 18:22:07 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
2004-06-03 20:46:20 +02:00
|
|
|
}
|
2013-01-24 00:04:02 +01:00
|
|
|
|
|
|
|
static const TypeInfo cuda_type_info = {
|
|
|
|
.name = TYPE_CUDA,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(CUDAState),
|
|
|
|
.instance_init = cuda_initfn,
|
|
|
|
.class_init = cuda_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void cuda_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&cuda_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(cuda_register_types)
|