hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation
PLLs are composed of multiple channels. Each channel outputs one clock signal. They are modeled as one device taking the PLL generated clock as input, and outputting a new clock. A channel shares the CM register with its parent PLL, and has its own A2W_CTRL register. A write to the CM register will trigger an update of the PLL and all its channels, while a write to an A2W_CTRL channel register will update the required channel only. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel
Peter Maydell
parent
6d2b874cf1
commit
09d56bbc9b
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@ -132,6 +132,69 @@ static const TypeInfo cprman_pll_info = {
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};
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/* PLL channel */
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static void pll_channel_update(CprmanPllChannelState *channel)
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{
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clock_update(channel->out, 0);
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}
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/* Update a PLL and all its channels */
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static void pll_update_all_channels(BCM2835CprmanState *s,
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CprmanPllState *pll)
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{
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size_t i;
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pll_update(pll);
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for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
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CprmanPllChannelState *channel = &s->channels[i];
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if (channel->parent == pll->id) {
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pll_channel_update(channel);
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}
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}
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}
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static void pll_channel_pll_in_update(void *opaque)
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{
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pll_channel_update(CPRMAN_PLL_CHANNEL(opaque));
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}
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static void pll_channel_init(Object *obj)
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{
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CprmanPllChannelState *s = CPRMAN_PLL_CHANNEL(obj);
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s->pll_in = qdev_init_clock_in(DEVICE(s), "pll-in",
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pll_channel_pll_in_update, s);
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription pll_channel_vmstate = {
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.name = TYPE_CPRMAN_PLL_CHANNEL,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_CLOCK(pll_in, CprmanPllChannelState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pll_channel_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &pll_channel_vmstate;
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}
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static const TypeInfo cprman_pll_channel_info = {
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.name = TYPE_CPRMAN_PLL_CHANNEL,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanPllChannelState),
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.class_init = pll_channel_class_init,
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.instance_init = pll_channel_init,
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};
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/* CPRMAN "top level" model */
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static uint32_t get_cm_lock(const BCM2835CprmanState *s)
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@ -174,8 +237,32 @@ static uint64_t cprman_read(void *opaque, hwaddr offset,
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return r;
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}
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#define CASE_PLL_REGS(pll_) \
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case R_CM_ ## pll_: \
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static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s,
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size_t idx)
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{
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size_t i;
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for (i = 0; i < CPRMAN_NUM_PLL; i++) {
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if (PLL_INIT_INFO[i].cm_offset == idx) {
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pll_update_all_channels(s, &s->plls[i]);
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return;
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}
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}
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}
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static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
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{
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size_t i;
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for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
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if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset == idx) {
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pll_channel_update(&s->channels[i]);
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return;
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}
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}
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}
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#define CASE_PLL_A2W_REGS(pll_) \
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case R_A2W_ ## pll_ ## _CTRL: \
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case R_A2W_ ## pll_ ## _ANA0: \
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case R_A2W_ ## pll_ ## _ANA1: \
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@ -200,29 +287,57 @@ static void cprman_write(void *opaque, hwaddr offset,
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s->regs[idx] = value;
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switch (idx) {
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CASE_PLL_REGS(PLLA) :
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case R_CM_PLLA ... R_CM_PLLH:
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case R_CM_PLLB:
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/*
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* A given CM_PLLx register is shared by both the PLL and the channels
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* of this PLL.
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*/
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update_pll_and_channels_from_cm(s, idx);
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break;
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CASE_PLL_A2W_REGS(PLLA) :
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pll_update(&s->plls[CPRMAN_PLLA]);
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break;
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CASE_PLL_REGS(PLLC) :
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CASE_PLL_A2W_REGS(PLLC) :
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pll_update(&s->plls[CPRMAN_PLLC]);
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break;
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CASE_PLL_REGS(PLLD) :
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CASE_PLL_A2W_REGS(PLLD) :
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pll_update(&s->plls[CPRMAN_PLLD]);
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break;
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CASE_PLL_REGS(PLLH) :
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CASE_PLL_A2W_REGS(PLLH) :
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pll_update(&s->plls[CPRMAN_PLLH]);
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break;
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CASE_PLL_REGS(PLLB) :
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CASE_PLL_A2W_REGS(PLLB) :
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pll_update(&s->plls[CPRMAN_PLLB]);
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break;
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case R_A2W_PLLA_DSI0:
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case R_A2W_PLLA_CORE:
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case R_A2W_PLLA_PER:
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case R_A2W_PLLA_CCP2:
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case R_A2W_PLLC_CORE2:
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case R_A2W_PLLC_CORE1:
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case R_A2W_PLLC_PER:
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case R_A2W_PLLC_CORE0:
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case R_A2W_PLLD_DSI0:
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case R_A2W_PLLD_CORE:
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case R_A2W_PLLD_PER:
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case R_A2W_PLLD_DSI1:
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case R_A2W_PLLH_AUX:
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case R_A2W_PLLH_RCAL:
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case R_A2W_PLLH_PIX:
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case R_A2W_PLLB_ARM:
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update_channel_from_a2w(s, idx);
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break;
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}
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}
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#undef CASE_PLL_REGS
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#undef CASE_PLL_A2W_REGS
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static const MemoryRegionOps cprman_ops = {
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.read = cprman_read,
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@ -254,6 +369,10 @@ static void cprman_reset(DeviceState *dev)
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device_cold_reset(DEVICE(&s->plls[i]));
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}
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for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
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device_cold_reset(DEVICE(&s->channels[i]));
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}
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clock_update_hz(s->xosc, s->xosc_freq);
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}
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@ -268,6 +387,13 @@ static void cprman_init(Object *obj)
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set_pll_init_info(s, &s->plls[i], i);
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}
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for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
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object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name,
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&s->channels[i],
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TYPE_CPRMAN_PLL_CHANNEL);
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set_pll_channel_init_info(s, &s->channels[i], i);
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}
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s->xosc = clock_new(obj, "xosc");
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memory_region_init_io(&s->iomem, obj, &cprman_ops,
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@ -289,6 +415,18 @@ static void cprman_realize(DeviceState *dev, Error **errp)
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return;
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}
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}
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for (i = 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) {
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CprmanPllChannelState *channel = &s->channels[i];
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CprmanPll parent = PLL_CHANNEL_INIT_INFO[i].parent;
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Clock *parent_clk = s->plls[parent].out;
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clock_set_source(channel->pll_in, parent_clk);
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if (!qdev_realize(DEVICE(channel), NULL, errp)) {
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return;
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}
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}
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}
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static const VMStateDescription cprman_vmstate = {
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@ -328,6 +466,7 @@ static void cprman_register_types(void)
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{
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type_register_static(&cprman_info);
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type_register_static(&cprman_pll_info);
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type_register_static(&cprman_pll_channel_info);
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}
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type_init(cprman_register_types);
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@ -31,6 +31,31 @@ typedef enum CprmanPll {
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CPRMAN_NUM_PLL
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} CprmanPll;
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typedef enum CprmanPllChannel {
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CPRMAN_PLLA_CHANNEL_DSI0 = 0,
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CPRMAN_PLLA_CHANNEL_CORE,
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CPRMAN_PLLA_CHANNEL_PER,
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CPRMAN_PLLA_CHANNEL_CCP2,
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CPRMAN_PLLC_CHANNEL_CORE2,
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CPRMAN_PLLC_CHANNEL_CORE1,
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CPRMAN_PLLC_CHANNEL_PER,
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CPRMAN_PLLC_CHANNEL_CORE0,
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CPRMAN_PLLD_CHANNEL_DSI0,
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CPRMAN_PLLD_CHANNEL_CORE,
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CPRMAN_PLLD_CHANNEL_PER,
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CPRMAN_PLLD_CHANNEL_DSI1,
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CPRMAN_PLLH_CHANNEL_AUX,
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CPRMAN_PLLH_CHANNEL_RCAL,
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CPRMAN_PLLH_CHANNEL_PIX,
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CPRMAN_PLLB_CHANNEL_ARM,
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CPRMAN_NUM_PLL_CHANNEL,
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} CprmanPllChannel;
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typedef struct CprmanPllState {
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/*< private >*/
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DeviceState parent_obj;
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@ -48,6 +73,24 @@ typedef struct CprmanPllState {
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Clock *out;
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} CprmanPllState;
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typedef struct CprmanPllChannelState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanPllChannel id;
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CprmanPll parent;
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uint32_t *reg_cm;
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uint32_t hold_mask;
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uint32_t load_mask;
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uint32_t *reg_a2w_ctrl;
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int fixed_divider;
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Clock *pll_in;
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Clock *out;
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} CprmanPllChannelState;
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struct BCM2835CprmanState {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -56,6 +99,7 @@ struct BCM2835CprmanState {
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MemoryRegion iomem;
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CprmanPllState plls[CPRMAN_NUM_PLL];
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CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
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uint32_t regs[CPRMAN_NUM_REGS];
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uint32_t xosc_freq;
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@ -13,9 +13,12 @@
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#include "hw/misc/bcm2835_cprman.h"
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#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
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#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
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DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
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TYPE_CPRMAN_PLL)
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DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
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TYPE_CPRMAN_PLL_CHANNEL)
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/* Register map */
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@ -100,6 +103,31 @@ REG32(A2W_PLLD_FRAC, 0x1240)
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REG32(A2W_PLLH_FRAC, 0x1260)
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REG32(A2W_PLLB_FRAC, 0x12e0)
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/* PLL channels */
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REG32(A2W_PLLA_DSI0, 0x1300)
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FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8)
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FIELD(A2W_PLLx_CHANNELy, DISABLE, 8, 1)
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REG32(A2W_PLLA_CORE, 0x1400)
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REG32(A2W_PLLA_PER, 0x1500)
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REG32(A2W_PLLA_CCP2, 0x1600)
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REG32(A2W_PLLC_CORE2, 0x1320)
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REG32(A2W_PLLC_CORE1, 0x1420)
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REG32(A2W_PLLC_PER, 0x1520)
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REG32(A2W_PLLC_CORE0, 0x1620)
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REG32(A2W_PLLD_DSI0, 0x1340)
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REG32(A2W_PLLD_CORE, 0x1440)
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REG32(A2W_PLLD_PER, 0x1540)
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REG32(A2W_PLLD_DSI1, 0x1640)
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REG32(A2W_PLLH_AUX, 0x1360)
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REG32(A2W_PLLH_RCAL, 0x1460)
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REG32(A2W_PLLH_PIX, 0x1560)
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REG32(A2W_PLLH_STS, 0x1660)
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REG32(A2W_PLLB_ARM, 0x13e0)
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/* misc registers */
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REG32(CM_LOCK, 0x114)
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FIELD(CM_LOCK, FLOCKH, 12, 1)
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@ -173,4 +201,122 @@ static inline void set_pll_init_info(BCM2835CprmanState *s,
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pll->reg_a2w_frac = &s->regs[PLL_INIT_INFO[id].a2w_frac_offset];
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}
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/* PLL channel init info */
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typedef struct PLLChannelInitInfo {
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const char *name;
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CprmanPll parent;
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size_t cm_offset;
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uint32_t cm_hold_mask;
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uint32_t cm_load_mask;
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size_t a2w_ctrl_offset;
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unsigned int fixed_divider;
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} PLLChannelInitInfo;
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#define FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_) \
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.parent = CPRMAN_ ## pll_, \
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.cm_offset = R_CM_ ## pll_, \
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.cm_load_mask = R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \
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.a2w_ctrl_offset = R_A2W_ ## pll_ ## _ ## channel_
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#define FILL_PLL_CHANNEL_INIT_INFO(pll_, channel_) \
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FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
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.cm_hold_mask = R_CM_ ## pll_ ## _ ## HOLD ## channel_ ## _MASK, \
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.fixed_divider = 1
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#define FILL_PLL_CHANNEL_INIT_INFO_nohold(pll_, channel_) \
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FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \
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.cm_hold_mask = 0
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static PLLChannelInitInfo PLL_CHANNEL_INIT_INFO[] = {
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[CPRMAN_PLLA_CHANNEL_DSI0] = {
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.name = "plla-dsi0",
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FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0),
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},
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[CPRMAN_PLLA_CHANNEL_CORE] = {
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.name = "plla-core",
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FILL_PLL_CHANNEL_INIT_INFO(PLLA, CORE),
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},
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[CPRMAN_PLLA_CHANNEL_PER] = {
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.name = "plla-per",
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FILL_PLL_CHANNEL_INIT_INFO(PLLA, PER),
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},
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[CPRMAN_PLLA_CHANNEL_CCP2] = {
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.name = "plla-ccp2",
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FILL_PLL_CHANNEL_INIT_INFO(PLLA, CCP2),
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},
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[CPRMAN_PLLC_CHANNEL_CORE2] = {
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.name = "pllc-core2",
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FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE2),
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},
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[CPRMAN_PLLC_CHANNEL_CORE1] = {
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.name = "pllc-core1",
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FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE1),
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},
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[CPRMAN_PLLC_CHANNEL_PER] = {
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.name = "pllc-per",
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FILL_PLL_CHANNEL_INIT_INFO(PLLC, PER),
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},
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[CPRMAN_PLLC_CHANNEL_CORE0] = {
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.name = "pllc-core0",
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FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE0),
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},
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[CPRMAN_PLLD_CHANNEL_DSI0] = {
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.name = "plld-dsi0",
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FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0),
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},
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[CPRMAN_PLLD_CHANNEL_CORE] = {
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.name = "plld-core",
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FILL_PLL_CHANNEL_INIT_INFO(PLLD, CORE),
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},
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[CPRMAN_PLLD_CHANNEL_PER] = {
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.name = "plld-per",
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FILL_PLL_CHANNEL_INIT_INFO(PLLD, PER),
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},
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[CPRMAN_PLLD_CHANNEL_DSI1] = {
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.name = "plld-dsi1",
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FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI1),
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},
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[CPRMAN_PLLH_CHANNEL_AUX] = {
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.name = "pllh-aux",
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.fixed_divider = 1,
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FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, AUX),
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},
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[CPRMAN_PLLH_CHANNEL_RCAL] = {
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.name = "pllh-rcal",
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.fixed_divider = 10,
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FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, RCAL),
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},
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[CPRMAN_PLLH_CHANNEL_PIX] = {
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.name = "pllh-pix",
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.fixed_divider = 10,
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FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, PIX),
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},
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[CPRMAN_PLLB_CHANNEL_ARM] = {
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.name = "pllb-arm",
|
||||
FILL_PLL_CHANNEL_INIT_INFO(PLLB, ARM),
|
||||
},
|
||||
};
|
||||
|
||||
#undef FILL_PLL_CHANNEL_INIT_INFO_nohold
|
||||
#undef FILL_PLL_CHANNEL_INIT_INFO
|
||||
#undef FILL_PLL_CHANNEL_INIT_INFO_common
|
||||
|
||||
static inline void set_pll_channel_init_info(BCM2835CprmanState *s,
|
||||
CprmanPllChannelState *channel,
|
||||
CprmanPllChannel id)
|
||||
{
|
||||
channel->id = id;
|
||||
channel->parent = PLL_CHANNEL_INIT_INFO[id].parent;
|
||||
channel->reg_cm = &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset];
|
||||
channel->hold_mask = PLL_CHANNEL_INIT_INFO[id].cm_hold_mask;
|
||||
channel->load_mask = PLL_CHANNEL_INIT_INFO[id].cm_load_mask;
|
||||
channel->reg_a2w_ctrl = &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_offset];
|
||||
channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue