target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present
If the floating point extension is present, then the SG instruction must clear the CONTROL_S.SFPA bit. Implement this. (On a no-FPU system the bit will always be zero, so we don't need to make the clearing of the bit conditional on ARM_FEATURE_VFP.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-8-peter.maydell@linaro.org
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@ -8804,6 +8804,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
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qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
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", executing it\n", env->regs[15]);
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env->regs[14] &= ~1;
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env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
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switch_v7m_security_state(env, true);
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xpsr_write(env, 0, XPSR_IT);
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env->regs[15] += 4;
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