target/arm: Decode FP instructions for M profile
Correct the decode of the M-profile "coprocessor and floating-point instructions" space: * op0 == 0b11 is always unallocated * if the CPU has an FPU then all insns with op1 == 0b101 are floating point and go to disas_vfp_insn() For the moment we leave VLLDM and VLSTM as NOPs; in a later commit we will fill in the proper implementation for the case where an FPU is present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190416125744.27770-7-peter.maydell@linaro.org
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@ -11728,10 +11728,19 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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case 6: case 7: case 14: case 15:
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/* Coprocessor. */
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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/* We don't currently implement M profile FP support,
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* so this entire space should give a NOCP fault, with
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* the exception of the v8M VLLDM and VLSTM insns, which
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* must be NOPs in Secure state and UNDEF in Nonsecure state.
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/* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */
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if (extract32(insn, 24, 2) == 3) {
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goto illegal_op; /* op0 = 0b11 : unallocated */
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}
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/*
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* Decode VLLDM and VLSTM first: these are nonstandard because:
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* * if there is no FPU then these insns must NOP in
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* Secure state and UNDEF in Nonsecure state
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* * if there is an FPU then these insns do not have
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* the usual behaviour that disas_vfp_insn() provides of
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* being controlled by CPACR/NSACR enable bits or the
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* lazy-stacking logic.
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*/
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if (arm_dc_feature(s, ARM_FEATURE_V8) &&
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(insn & 0xffa00f00) == 0xec200a00) {
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@ -11745,6 +11754,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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/* Just NOP since FP support is not implemented */
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break;
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}
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if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
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((insn >> 8) & 0xe) == 10) {
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/* FP, and the CPU supports it */
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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break;
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}
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/* All other insns: NOCP */
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gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
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default_exception_el(s));
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