target/ppc: Split out gen_ld_atomic
Move the guts of LD_ATOMIC to a function. Use foo_tl for the operations instead of foo_i32 or foo_i64 specifically. Use MO_ALIGN instead of an explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3095,61 +3095,60 @@ LARX(lbarx, DEF_MEMOP(MO_UB))
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LARX(lharx, DEF_MEMOP(MO_UW))
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LARX(lwarx, DEF_MEMOP(MO_UL))
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#define LD_ATOMIC(name, memop, tp, op, eop) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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int len = MEMOP_GET_SIZE(memop); \
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uint32_t gpr_FC = FC(ctx->opcode); \
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TCGv EA = tcg_temp_local_new(); \
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TCGv_##tp t0, t1; \
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\
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gen_addr_register(ctx, EA); \
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if (len > 1) { \
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gen_check_align(ctx, EA, len - 1); \
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} \
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t0 = tcg_temp_new_##tp(); \
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t1 = tcg_temp_new_##tp(); \
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tcg_gen_##op(t0, cpu_gpr[rD(ctx->opcode) + 1]); \
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\
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switch (gpr_FC) { \
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case 0: /* Fetch and add */ \
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tcg_gen_atomic_fetch_add_##tp(t1, EA, t0, ctx->mem_idx, memop); \
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break; \
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case 1: /* Fetch and xor */ \
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tcg_gen_atomic_fetch_xor_##tp(t1, EA, t0, ctx->mem_idx, memop); \
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break; \
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case 2: /* Fetch and or */ \
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tcg_gen_atomic_fetch_or_##tp(t1, EA, t0, ctx->mem_idx, memop); \
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break; \
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case 3: /* Fetch and 'and' */ \
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tcg_gen_atomic_fetch_and_##tp(t1, EA, t0, ctx->mem_idx, memop); \
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break; \
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case 8: /* Swap */ \
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tcg_gen_atomic_xchg_##tp(t1, EA, t0, ctx->mem_idx, memop); \
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break; \
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case 4: /* Fetch and max unsigned */ \
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case 5: /* Fetch and max signed */ \
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case 6: /* Fetch and min unsigned */ \
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case 7: /* Fetch and min signed */ \
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case 16: /* compare and swap not equal */ \
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case 24: /* Fetch and increment bounded */ \
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case 25: /* Fetch and increment equal */ \
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case 28: /* Fetch and decrement bounded */ \
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gen_invalid(ctx); \
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break; \
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default: \
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/* invoke data storage error handler */ \
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gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); \
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} \
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tcg_gen_##eop(cpu_gpr[rD(ctx->opcode)], t1); \
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tcg_temp_free_##tp(t0); \
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tcg_temp_free_##tp(t1); \
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tcg_temp_free(EA); \
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static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop)
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{
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uint32_t gpr_FC = FC(ctx->opcode);
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TCGv EA = tcg_temp_new();
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TCGv src, dst;
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gen_addr_register(ctx, EA);
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dst = cpu_gpr[rD(ctx->opcode)];
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src = cpu_gpr[rD(ctx->opcode) + 1];
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memop |= MO_ALIGN;
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switch (gpr_FC) {
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case 0: /* Fetch and add */
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tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop);
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break;
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case 1: /* Fetch and xor */
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tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop);
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break;
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case 2: /* Fetch and or */
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tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop);
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break;
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case 3: /* Fetch and 'and' */
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tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop);
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break;
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case 8: /* Swap */
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tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop);
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break;
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case 4: /* Fetch and max unsigned */
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case 5: /* Fetch and max signed */
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case 6: /* Fetch and min unsigned */
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case 7: /* Fetch and min signed */
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case 16: /* compare and swap not equal */
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case 24: /* Fetch and increment bounded */
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case 25: /* Fetch and increment equal */
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case 28: /* Fetch and decrement bounded */
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gen_invalid(ctx);
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break;
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default:
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/* invoke data storage error handler */
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gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL);
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}
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tcg_temp_free(EA);
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}
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LD_ATOMIC(lwat, DEF_MEMOP(MO_UL), i32, trunc_tl_i32, extu_i32_tl)
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#if defined(TARGET_PPC64)
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LD_ATOMIC(ldat, DEF_MEMOP(MO_Q), i64, mov_i64, mov_i64)
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static void gen_lwat(DisasContext *ctx)
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{
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gen_ld_atomic(ctx, DEF_MEMOP(MO_UL));
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}
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#ifdef TARGET_PPC64
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static void gen_ldat(DisasContext *ctx)
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{
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gen_ld_atomic(ctx, DEF_MEMOP(MO_Q));
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}
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#endif
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#define ST_ATOMIC(name, memop, tp, op) \
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