target/ppc: Split out gen_load_locked
Leave only the minimal amount of code within the LDAR macro, moving the rest of the code into gen_load_locked. Use MO_ALIGN and remove the explicit call to gen_check_align. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3070,23 +3070,24 @@ static void gen_isync(DisasContext *ctx)
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#define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
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#define LARX(name, memop) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv t0; \
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TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
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int len = MEMOP_GET_SIZE(memop); \
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gen_set_access_type(ctx, ACCESS_RES); \
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t0 = tcg_temp_local_new(); \
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gen_addr_reg_index(ctx, t0); \
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if ((len) > 1) { \
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gen_check_align(ctx, t0, (len)-1); \
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} \
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tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
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tcg_gen_mov_tl(cpu_reserve, t0); \
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tcg_gen_mov_tl(cpu_reserve_val, gpr); \
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
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tcg_temp_free(t0); \
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static void gen_load_locked(DisasContext *ctx, TCGMemOp memop)
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{
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TCGv gpr = cpu_gpr[rD(ctx->opcode)];
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TCGv t0 = tcg_temp_new();
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gen_set_access_type(ctx, ACCESS_RES);
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gen_addr_reg_index(ctx, t0);
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tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN);
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tcg_gen_mov_tl(cpu_reserve, t0);
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tcg_gen_mov_tl(cpu_reserve_val, gpr);
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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tcg_temp_free(t0);
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}
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#define LARX(name, memop) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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gen_load_locked(ctx, memop); \
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}
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/* lwarx */
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