target-ppc: consolidate store conditional
Use tcg_gen_qemu_st store conditional instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -3076,19 +3076,19 @@ LARX(lwarx, DEF_MEMOP(MO_UL))
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#if defined(CONFIG_USER_ONLY)
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static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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int reg, int size)
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int reg, int memop)
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{
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TCGv t0 = tcg_temp_new();
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tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
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tcg_gen_movi_tl(t0, (size << 5) | reg);
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tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg);
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tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
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tcg_temp_free(t0);
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gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
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}
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#else
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static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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int reg, int size)
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int reg, int memop)
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{
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TCGLabel *l1;
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@ -3096,44 +3096,36 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
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l1 = gen_new_label();
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tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
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tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
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#if defined(TARGET_PPC64)
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if (size == 8) {
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gen_qemu_st64_i64(ctx, cpu_gpr[reg], EA);
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} else
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#endif
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if (size == 4) {
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gen_qemu_st32(ctx, cpu_gpr[reg], EA);
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} else if (size == 2) {
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gen_qemu_st16(ctx, cpu_gpr[reg], EA);
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} else {
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gen_qemu_st8(ctx, cpu_gpr[reg], EA);
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}
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tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
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gen_set_label(l1);
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tcg_gen_movi_tl(cpu_reserve, -1);
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}
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#endif
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#define STCX(name, len) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv t0; \
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gen_set_access_type(ctx, ACCESS_RES); \
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t0 = tcg_temp_local_new(); \
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gen_addr_reg_index(ctx, t0); \
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if (len > 1) { \
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gen_check_align(ctx, t0, (len)-1); \
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} \
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gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
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tcg_temp_free(t0); \
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#define STCX(name, memop) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv t0; \
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int len = MEMOP_GET_SIZE(memop); \
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gen_set_access_type(ctx, ACCESS_RES); \
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t0 = tcg_temp_local_new(); \
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gen_addr_reg_index(ctx, t0); \
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if (len > 1) { \
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gen_check_align(ctx, t0, (len) - 1); \
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} \
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gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \
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tcg_temp_free(t0); \
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}
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STCX(stbcx_, 1);
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STCX(sthcx_, 2);
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STCX(stwcx_, 4);
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STCX(stbcx_, DEF_MEMOP(MO_UB))
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STCX(sthcx_, DEF_MEMOP(MO_UW))
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STCX(stwcx_, DEF_MEMOP(MO_UL))
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#if defined(TARGET_PPC64)
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/* ldarx */
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LARX(ldarx, DEF_MEMOP(MO_Q))
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/* stdcx. */
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STCX(stdcx_, DEF_MEMOP(MO_Q))
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/* lqarx */
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static void gen_lqarx(DisasContext *ctx)
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@ -3216,8 +3208,6 @@ static void gen_stqcx_(DisasContext *ctx)
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tcg_temp_free(EA);
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}
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/* stdcx. */
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STCX(stdcx_, 8);
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#endif /* defined(TARGET_PPC64) */
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/* sync */
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