target/mips: Clean up handling of CP0 register 1
Clean up handling of CP0 register 1. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-3-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -282,6 +282,14 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG00__MVPCONF1 3
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#define CP0_REG00__VPCONTROL 4
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/* CP0 Register 01 */
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#define CP0_REG01__RANDOM 0
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#define CP0_REG01__VPECONTROL 1
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#define CP0_REG01__VPECONF0 2
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#define CP0_REG01__VPECONF1 3
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#define CP0_REG01__YQMASK 4
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#define CP0_REG01__VPESCHEDULE 5
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#define CP0_REG01__VPESCHEFBACK 6
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#define CP0_REG01__VPEOPT 7
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/* CP0 Register 02 */
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#define CP0_REG02__ENTRYLO0 0
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/* CP0 Register 03 */
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@ -6843,42 +6843,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_01:
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switch (sel) {
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case 0:
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case CP0_REG01__RANDOM:
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CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
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gen_helper_mfc0_random(arg, cpu_env);
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register_name = "Random";
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break;
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case 1:
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case CP0_REG01__VPECONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
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register_name = "VPEControl";
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break;
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case 2:
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case CP0_REG01__VPECONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
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register_name = "VPEConf0";
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break;
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case 3:
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case CP0_REG01__VPECONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
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register_name = "VPEConf1";
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break;
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case 4:
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case CP0_REG01__YQMASK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
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register_name = "YQMask";
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break;
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case 5:
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case CP0_REG01__VPESCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
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register_name = "VPESchedule";
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break;
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case 6:
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case CP0_REG01__VPESCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
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register_name = "VPEScheFBack";
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break;
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case 7:
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case CP0_REG01__VPEOPT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
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register_name = "VPEOpt";
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@ -7603,43 +7603,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_01:
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switch (sel) {
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case 0:
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case CP0_REG01__RANDOM:
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/* ignored */
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register_name = "Random";
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break;
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case 1:
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case CP0_REG01__VPECONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpecontrol(cpu_env, arg);
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register_name = "VPEControl";
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break;
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case 2:
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case CP0_REG01__VPECONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpeconf0(cpu_env, arg);
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register_name = "VPEConf0";
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break;
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case 3:
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case CP0_REG01__VPECONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpeconf1(cpu_env, arg);
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register_name = "VPEConf1";
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break;
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case 4:
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case CP0_REG01__YQMASK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_yqmask(cpu_env, arg);
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register_name = "YQMask";
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break;
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case 5:
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case CP0_REG01__VPESCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_st_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_VPESchedule));
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register_name = "VPESchedule";
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break;
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case 6:
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case CP0_REG01__VPESCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_st_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_VPEScheFBack));
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register_name = "VPEScheFBack";
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break;
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case 7:
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case CP0_REG01__VPEOPT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpeopt(cpu_env, arg);
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register_name = "VPEOpt";
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@ -8349,42 +8349,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_01:
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switch (sel) {
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case 0:
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case CP0_REG01__RANDOM:
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CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
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gen_helper_mfc0_random(arg, cpu_env);
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register_name = "Random";
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break;
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case 1:
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case CP0_REG01__VPECONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
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register_name = "VPEControl";
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break;
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case 2:
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case CP0_REG01__VPECONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
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register_name = "VPEConf0";
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break;
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case 3:
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case CP0_REG01__VPECONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
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register_name = "VPEConf1";
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break;
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case 4:
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case CP0_REG01__YQMASK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
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register_name = "YQMask";
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break;
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case 5:
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case CP0_REG01__VPESCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
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register_name = "VPESchedule";
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break;
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case 6:
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case CP0_REG01__VPESCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
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register_name = "VPEScheFBack";
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break;
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case 7:
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case CP0_REG01__VPEOPT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
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register_name = "VPEOpt";
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@ -9063,41 +9063,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_01:
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switch (sel) {
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case 0:
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case CP0_REG01__RANDOM:
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/* ignored */
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register_name = "Random";
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break;
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case 1:
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case CP0_REG01__VPECONTROL:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpecontrol(cpu_env, arg);
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register_name = "VPEControl";
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break;
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case 2:
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case CP0_REG01__VPECONF0:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpeconf0(cpu_env, arg);
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register_name = "VPEConf0";
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break;
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case 3:
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case CP0_REG01__VPECONF1:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpeconf1(cpu_env, arg);
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register_name = "VPEConf1";
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break;
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case 4:
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case CP0_REG01__YQMASK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_yqmask(cpu_env, arg);
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register_name = "YQMask";
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break;
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case 5:
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case CP0_REG01__VPESCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
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register_name = "VPESchedule";
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break;
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case 6:
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case CP0_REG01__VPESCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
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register_name = "VPEScheFBack";
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break;
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case 7:
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case CP0_REG01__VPEOPT:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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gen_helper_mtc0_vpeopt(cpu_env, arg);
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register_name = "VPEOpt";
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