net: xilinx_ethlite: Fix Rx-pong interrupt
There is no CTRL_I bit in the pong buffer control register. The CTRL_I bit from the ping buffer masks both ping and pong buffers. Fix. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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@ -196,8 +196,9 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
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memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
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memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size);
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s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
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s->regs[rxbase + R_RX_CTRL0] |= CTRL_S;
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if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I)
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if (s->regs[R_RX_CTRL0] & CTRL_I) {
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eth_pulse_irq(s);
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eth_pulse_irq(s);
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}
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/* If c_rx_pingpong was set flip buffers. */
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/* If c_rx_pingpong was set flip buffers. */
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s->rxbuf ^= s->c_rx_pingpong;
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s->rxbuf ^= s->c_rx_pingpong;
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