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qemu-patch-raspberry4
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target/riscv: Calculate address according to XLEN 

Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
staging
LIU Zhiwei 2022-01-20 20:20:40 +08:00 committed by Alistair Francis
parent 0cff460de9
commit 4302bef9e1
5 changed files with 21 additions and 69 deletions
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9
target/riscv/insn_trans/trans_rva.c.inc
View File

@ -20,12 +20,11 @@
static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
TCGv src1 = get_address(ctx, a->rs1, 0);
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
src1 = gen_pm_adjust_address(ctx, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@ -44,8 +43,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
src1 = gen_pm_adjust_address(ctx, src1);
src1 = get_address(ctx, a->rs1, 0);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
/*
@ -83,10 +81,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
MemOp mop)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv src1 = get_address(ctx, a->rs1, 0);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
src1 = gen_pm_adjust_address(ctx, src1);
func(dest, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(ctx, a->rd, dest);

19
target/riscv/insn_trans/trans_rvd.c.inc
View File

@ -25,14 +25,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
addr = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ);
mark_fs_dirty(ctx);
@ -46,16 +39,8 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
addr = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ);
return true;
}

19
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -31,14 +31,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
addr = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
addr = get_address(ctx, a->rs1, a->imm);
dest = cpu_fpr[a->rd];
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
gen_nanbox_s(dest, dest);
@ -54,16 +47,8 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
addr = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = tcg_temp_new();
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
return true;
}

18
target/riscv/insn_trans/trans_rvi.c.inc
View File

@ -226,14 +226,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
TCGv addr = get_address(ctx, a->rs1, a->imm);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest);
@ -330,16 +323,9 @@ static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv addr = get_address(ctx, a->rs1, a->imm);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
if (a->imm) {
TCGv temp = temp_new(ctx);
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
}

25
target/riscv/translate.c
View File

@ -390,21 +390,20 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
/*
* Generates address adjustment for PointerMasking
*/
static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
/* Compute a canonical address from a register plus offset. */
static TCGv get_address(DisasContext *ctx, int rs1, int imm)
{
TCGv temp;
if (!s->pm_enabled) {
/* Load unmodified address */
return src;
} else {
temp = temp_new(s);
tcg_gen_andc_tl(temp, src, pm_mask);
tcg_gen_or_tl(temp, temp, pm_base);
return temp;
TCGv addr = temp_new(ctx);
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
if (ctx->pm_enabled) {
tcg_gen_and_tl(addr, addr, pm_mask);
tcg_gen_or_tl(addr, addr, pm_base);
} else if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
return addr;
}
#ifndef CONFIG_USER_ONLY