No functional changes:
- compilation warning fixes - make loglevel tests consistent - use cpu_abort instead of printf(...); exit git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2706 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
0405f55b57
commit
4a0577124a
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@ -59,9 +59,6 @@ CPUState *ppc405_init (const unsigned char *cpu_model,
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uint32_t sysclk);
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uint32_t sysclk);
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
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ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd);
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void ppc40x_core_reset (CPUState *env);
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void ppc40x_chip_reset (CPUState *env);
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void ppc40x_system_reset (CPUState *env);
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/* */
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/* */
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typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
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typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
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@ -349,11 +349,11 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
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cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
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exit(1);
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exit(1);
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}
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}
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bios_size = (bios_size + 0xfff) & ~0xfff;
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bios_size = (bios_size + 0xfff) & ~0xfff;
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cpu_register_physical_memory((uint32_t)(-bios_size),
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cpu_register_physical_memory((uint32_t)(-bios_size),
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bios_size, bios_offset | IO_MEM_ROM);
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bios_size, bios_offset | IO_MEM_ROM);
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/* allocate and load VGA BIOS */
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/* allocate and load VGA BIOS */
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@ -382,8 +382,8 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
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/* now we can load the kernel */
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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cpu_abort(env, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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kernel_filename);
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exit(1);
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exit(1);
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}
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}
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/* load initrd */
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/* load initrd */
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@ -392,8 +392,8 @@ static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
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initrd_size = load_image(initrd_filename,
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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initrd_filename);
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exit(1);
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exit(1);
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}
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}
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} else {
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} else {
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@ -560,11 +560,11 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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if (bios_size < 0 || bios_size > BIOS_SIZE) {
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fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
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cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
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exit(1);
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exit(1);
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}
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}
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bios_size = (bios_size + 0xfff) & ~0xfff;
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bios_size = (bios_size + 0xfff) & ~0xfff;
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cpu_register_physical_memory((uint32_t)(-bios_size),
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cpu_register_physical_memory((uint32_t)(-bios_size),
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bios_size, bios_offset | IO_MEM_ROM);
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bios_size, bios_offset | IO_MEM_ROM);
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if (linux_boot) {
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if (linux_boot) {
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@ -572,8 +572,8 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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/* now we can load the kernel */
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/* now we can load the kernel */
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
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if (kernel_size < 0) {
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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cpu_abort(env, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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kernel_filename);
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exit(1);
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exit(1);
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}
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}
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/* load initrd */
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/* load initrd */
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@ -582,8 +582,8 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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initrd_size = load_image(initrd_filename,
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initrd_size = load_image(initrd_filename,
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phys_ram_base + initrd_base);
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phys_ram_base + initrd_base);
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if (initrd_size < 0) {
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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initrd_filename);
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exit(1);
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exit(1);
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}
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}
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} else {
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} else {
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@ -627,7 +627,8 @@ static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
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|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
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isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
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isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
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} else {
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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/* Why ? */
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cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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exit (1);
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}
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}
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}
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}
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@ -124,14 +124,14 @@ static int pte_check (mmu_ctx_t *ctx,
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(rw == 1 && (access & PAGE_WRITE))) {
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(rw == 1 && (access & PAGE_WRITE))) {
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/* Access granted */
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/* Access granted */
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "PTE access granted !\n");
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fprintf(logfile, "PTE access granted !\n");
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#endif
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#endif
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ret = 0;
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ret = 0;
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} else {
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} else {
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/* Access right violation */
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/* Access right violation */
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "PTE access rejected\n");
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fprintf(logfile, "PTE access rejected\n");
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#endif
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#endif
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ret = -2;
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ret = -2;
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@ -214,10 +214,10 @@ static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
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target_ulong eaddr,
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target_ulong eaddr,
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int is_code, int match_epn)
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int is_code, int match_epn)
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{
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{
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#if !defined(FLUSH_ALL_TLBS)
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ppc6xx_tlb_t *tlb;
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ppc6xx_tlb_t *tlb;
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int way, nr;
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int way, nr;
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#if !defined(FLUSH_ALL_TLBS)
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/* Invalidate ITLB + DTLB, all ways */
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/* Invalidate ITLB + DTLB, all ways */
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for (way = 0; way < env->nb_ways; way++) {
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for (way = 0; way < env->nb_ways; way++) {
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
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nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
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@ -331,7 +331,7 @@ static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
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if (best != -1) {
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if (best != -1) {
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done:
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done:
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#if defined (DEBUG_SOFTWARE_TLB)
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
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fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
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}
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}
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@ -353,7 +353,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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int ret = -1;
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int ret = -1;
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#if defined (DEBUG_BATS)
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
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fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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}
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}
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@ -369,7 +369,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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break;
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break;
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}
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}
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#if defined (DEBUG_BATS)
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
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fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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type == ACCESS_CODE ? 'I' : 'D', virtual);
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}
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}
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@ -382,7 +382,7 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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BEPIl = *BATu & 0x0FFE0000;
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BEPIl = *BATu & 0x0FFE0000;
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bl = (*BATu & 0x00001FFC) << 15;
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bl = (*BATu & 0x00001FFC) << 15;
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#if defined (DEBUG_BATS)
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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" BATl 0x" ADDRX "\n",
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" BATl 0x" ADDRX "\n",
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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@ -403,8 +403,8 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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if (*BATl & 0x00000002)
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if (*BATl & 0x00000002)
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ctx->prot = PAGE_WRITE | PAGE_READ;
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ctx->prot = PAGE_WRITE | PAGE_READ;
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#if defined (DEBUG_BATS)
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#if defined (DEBUG_BATS)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "BAT %d match: r 0x" ADDRX
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fprintf(logfile, "BAT %d match: r 0x" PADDRX
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" prot=%c%c\n",
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" prot=%c%c\n",
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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ctx->prot & PAGE_WRITE ? 'W' : '-');
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@ -417,18 +417,20 @@ static int get_bat (CPUState *env, mmu_ctx_t *ctx,
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}
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}
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if (ret < 0) {
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if (ret < 0) {
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#if defined (DEBUG_BATS)
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#if defined (DEBUG_BATS)
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printf("no BAT match for 0x" ADDRX ":\n", virtual);
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if (loglevel != 0) {
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for (i = 0; i < 4; i++) {
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fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
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BATu = &BATut[i];
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for (i = 0; i < 4; i++) {
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BATl = &BATlt[i];
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BATu = &BATut[i];
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BEPIu = *BATu & 0xF0000000;
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BATl = &BATlt[i];
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BEPIl = *BATu & 0x0FFE0000;
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BEPIu = *BATu & 0xF0000000;
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bl = (*BATu & 0x00001FFC) << 15;
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BEPIl = *BATu & 0x0FFE0000;
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printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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bl = (*BATu & 0x00001FFC) << 15;
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" BATl 0x" ADDRX " \n\t"
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fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
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"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
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" BATl 0x" ADDRX " \n\t"
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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"0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
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*BATu, *BATl, BEPIu, BEPIl, bl);
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__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
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*BATu, *BATl, BEPIu, BEPIl, bl);
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}
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}
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}
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#endif
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#endif
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}
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}
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@ -483,8 +485,8 @@ static int find_pte (mmu_ctx_t *ctx, int h, int rw)
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if (good != -1) {
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if (good != -1) {
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done:
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done:
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x "
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fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
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"ret=%d\n",
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"ret=%d\n",
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ctx->raddr, ctx->prot, ret);
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ctx->raddr, ctx->prot, ret);
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}
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}
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@ -551,10 +553,11 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
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ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
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} else {
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} else {
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (loglevel > 0) {
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if (loglevel != 0) {
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fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x "
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fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
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"api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n",
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"api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
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sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
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sdr, (uint32_t)vsid, (uint32_t)pgidx,
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(uint32_t)hash, ctx->pg_addr[0]);
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}
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}
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#endif
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#endif
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/* Primary table lookup */
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/* Primary table lookup */
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@ -562,11 +565,12 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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if (ret < 0) {
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if (ret < 0) {
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/* Secondary table lookup */
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/* Secondary table lookup */
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (eaddr != 0xEFFFFFFF && loglevel > 0) {
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if (eaddr != 0xEFFFFFFF && loglevel != 0) {
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fprintf(logfile,
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fprintf(logfile,
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"1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x "
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"1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
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"hash=0x%05x pg_addr=0x" ADDRX "\n",
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"hash=0x%05x pg_addr=0x" PADDRX "\n",
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sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
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sdr, (uint32_t)vsid, (uint32_t)pgidx,
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(uint32_t)hash, ctx->pg_addr[1]);
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}
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}
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#endif
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#endif
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ret2 = find_pte(ctx, 1, rw);
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ret2 = find_pte(ctx, 1, rw);
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@ -576,14 +580,14 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
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}
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}
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} else {
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} else {
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "No access allowed\n");
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fprintf(logfile, "No access allowed\n");
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#endif
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#endif
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ret = -3;
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ret = -3;
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}
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}
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} else {
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} else {
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#if defined (DEBUG_MMU)
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#if defined (DEBUG_MMU)
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if (loglevel > 0)
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if (loglevel != 0)
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fprintf(logfile, "direct store...\n");
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fprintf(logfile, "direct store...\n");
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#endif
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#endif
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/* Direct-store segment : absolutely *BUGGY* for now */
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/* Direct-store segment : absolutely *BUGGY* for now */
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||||||
|
@ -615,8 +619,6 @@ static int get_segment (CPUState *env, mmu_ctx_t *ctx,
|
||||||
fprintf(logfile, "ERROR: instruction should not need "
|
fprintf(logfile, "ERROR: instruction should not need "
|
||||||
"address translation\n");
|
"address translation\n");
|
||||||
}
|
}
|
||||||
printf("ERROR: instruction should not need "
|
|
||||||
"address translation\n");
|
|
||||||
return -4;
|
return -4;
|
||||||
}
|
}
|
||||||
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
|
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
|
||||||
|
@ -663,12 +665,12 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
||||||
tlb = &env->tlb[i].tlbe;
|
tlb = &env->tlb[i].tlbe;
|
||||||
/* Check valid flag */
|
/* Check valid flag */
|
||||||
if (!(tlb->prot & PAGE_VALID)) {
|
if (!(tlb->prot & PAGE_VALID)) {
|
||||||
if (loglevel)
|
if (loglevel != 0)
|
||||||
fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
mask = ~(tlb->size - 1);
|
mask = ~(tlb->size - 1);
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
|
fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
|
||||||
ADDRX " " ADDRX " %d\n",
|
ADDRX " " ADDRX " %d\n",
|
||||||
__func__, i, address, (int)env->spr[SPR_40x_PID],
|
__func__, i, address, (int)env->spr[SPR_40x_PID],
|
||||||
|
@ -683,7 +685,7 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
||||||
raddr = (tlb->RPN & mask) | (address & ~mask);
|
raddr = (tlb->RPN & mask) | (address & ~mask);
|
||||||
zsel = (tlb->attr >> 4) & 0xF;
|
zsel = (tlb->attr >> 4) & 0xF;
|
||||||
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
|
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
|
||||||
__func__, i, zsel, zpr, rw, tlb->attr);
|
__func__, i, zsel, zpr, rw, tlb->attr);
|
||||||
}
|
}
|
||||||
|
@ -750,7 +752,7 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
||||||
}
|
}
|
||||||
if (ret >= 0) {
|
if (ret >= 0) {
|
||||||
ctx->raddr = raddr;
|
ctx->raddr = raddr;
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "%s: access granted " ADDRX " => " REGX
|
fprintf(logfile, "%s: access granted " ADDRX " => " REGX
|
||||||
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
|
||||||
ret);
|
ret);
|
||||||
|
@ -758,7 +760,7 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "%s: access refused " ADDRX " => " REGX
|
fprintf(logfile, "%s: access refused " ADDRX " => " REGX
|
||||||
" %d %d\n", __func__, address, raddr, ctx->prot,
|
" %d %d\n", __func__, address, raddr, ctx->prot,
|
||||||
ret);
|
ret);
|
||||||
|
@ -808,7 +810,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
||||||
{
|
{
|
||||||
int ret;
|
int ret;
|
||||||
#if 0
|
#if 0
|
||||||
if (loglevel > 0) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "%s\n", __func__);
|
fprintf(logfile, "%s\n", __func__);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -857,8 +859,8 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#if 0
|
#if 0
|
||||||
if (loglevel > 0) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "%s address " ADDRX " => %d " ADDRX "\n",
|
fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
|
||||||
__func__, eaddr, ret, ctx->raddr);
|
__func__, eaddr, ret, ctx->raddr);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -903,7 +905,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
|
||||||
is_user, is_softmmu);
|
is_user, is_softmmu);
|
||||||
} else if (ret < 0) {
|
} else if (ret < 0) {
|
||||||
#if defined (DEBUG_MMU)
|
#if defined (DEBUG_MMU)
|
||||||
if (loglevel > 0)
|
if (loglevel != 0)
|
||||||
cpu_dump_state(env, logfile, fprintf, 0);
|
cpu_dump_state(env, logfile, fprintf, 0);
|
||||||
#endif
|
#endif
|
||||||
if (access_type == ACCESS_CODE) {
|
if (access_type == ACCESS_CODE) {
|
||||||
|
@ -1564,7 +1566,7 @@ void do_interrupt (CPUState *env)
|
||||||
idx = 2;
|
idx = 2;
|
||||||
msr &= ~0xFFFF0000;
|
msr &= ~0xFFFF0000;
|
||||||
#if defined (DEBUG_EXCEPTIONS)
|
#if defined (DEBUG_EXCEPTIONS)
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
|
fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
|
||||||
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
"\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
|
||||||
}
|
}
|
||||||
|
@ -1609,7 +1611,7 @@ void do_interrupt (CPUState *env)
|
||||||
case EXCP_FP:
|
case EXCP_FP:
|
||||||
if (msr_fe0 == 0 && msr_fe1 == 0) {
|
if (msr_fe0 == 0 && msr_fe1 == 0) {
|
||||||
#if defined (DEBUG_EXCEPTIONS)
|
#if defined (DEBUG_EXCEPTIONS)
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "Ignore floating point exception\n");
|
fprintf(logfile, "Ignore floating point exception\n");
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -1625,7 +1627,7 @@ void do_interrupt (CPUState *env)
|
||||||
break;
|
break;
|
||||||
case EXCP_INVAL:
|
case EXCP_INVAL:
|
||||||
#if defined (DEBUG_EXCEPTIONS)
|
#if defined (DEBUG_EXCEPTIONS)
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
|
fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
|
||||||
env->nip);
|
env->nip);
|
||||||
}
|
}
|
||||||
|
@ -1836,7 +1838,7 @@ void do_interrupt (CPUState *env)
|
||||||
cmp = &env->spr[SPR_DCMP];
|
cmp = &env->spr[SPR_DCMP];
|
||||||
}
|
}
|
||||||
fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
|
fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
|
||||||
" H1 " ADDRX " H2 " ADDRX " " ADDRX "\n",
|
" H1 " ADDRX " H2 " ADDRX " %08x\n",
|
||||||
es, en, *miss, en, *cmp,
|
es, en, *miss, en, *cmp,
|
||||||
env->spr[SPR_HASH1], env->spr[SPR_HASH2],
|
env->spr[SPR_HASH1], env->spr[SPR_HASH2],
|
||||||
env->error_code);
|
env->error_code);
|
||||||
|
@ -2153,7 +2155,21 @@ void cpu_dump_EA (target_ulong EA)
|
||||||
f = stdout;
|
f = stdout;
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
|
fprintf(f, "Memory access at address " ADDRX "\n", EA);
|
||||||
|
}
|
||||||
|
|
||||||
|
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
|
||||||
|
{
|
||||||
|
FILE *f;
|
||||||
|
|
||||||
|
if (logfile) {
|
||||||
|
f = logfile;
|
||||||
|
} else {
|
||||||
|
f = stdout;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
|
||||||
|
RA, msr);
|
||||||
}
|
}
|
||||||
|
|
||||||
void cpu_ppc_reset (void *opaque)
|
void cpu_ppc_reset (void *opaque)
|
||||||
|
|
|
@ -3025,7 +3025,7 @@ static inline void gen_op_mfspr (DisasContext *ctx)
|
||||||
gen_op_store_T0_gpr(rD(ctx->opcode));
|
gen_op_store_T0_gpr(rD(ctx->opcode));
|
||||||
} else {
|
} else {
|
||||||
/* Privilege exception */
|
/* Privilege exception */
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "Trying to read priviledged spr %d %03x\n",
|
fprintf(logfile, "Trying to read priviledged spr %d %03x\n",
|
||||||
sprn, sprn);
|
sprn, sprn);
|
||||||
}
|
}
|
||||||
|
@ -3034,7 +3034,7 @@ static inline void gen_op_mfspr (DisasContext *ctx)
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
/* Not defined */
|
/* Not defined */
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "Trying to read invalid spr %d %03x\n",
|
fprintf(logfile, "Trying to read invalid spr %d %03x\n",
|
||||||
sprn, sprn);
|
sprn, sprn);
|
||||||
}
|
}
|
||||||
|
@ -3131,7 +3131,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
|
||||||
(*write_cb)(ctx, sprn);
|
(*write_cb)(ctx, sprn);
|
||||||
} else {
|
} else {
|
||||||
/* Privilege exception */
|
/* Privilege exception */
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "Trying to write priviledged spr %d %03x\n",
|
fprintf(logfile, "Trying to write priviledged spr %d %03x\n",
|
||||||
sprn, sprn);
|
sprn, sprn);
|
||||||
}
|
}
|
||||||
|
@ -3140,7 +3140,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
/* Not defined */
|
/* Not defined */
|
||||||
if (loglevel) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "Trying to write invalid spr %d %03x\n",
|
fprintf(logfile, "Trying to write invalid spr %d %03x\n",
|
||||||
sprn, sprn);
|
sprn, sprn);
|
||||||
}
|
}
|
||||||
|
@ -3378,7 +3378,7 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
|
||||||
RET_PRIVOPC(ctx);
|
RET_PRIVOPC(ctx);
|
||||||
#else
|
#else
|
||||||
if (unlikely(!ctx->supervisor)) {
|
if (unlikely(!ctx->supervisor)) {
|
||||||
if (loglevel)
|
if (loglevel != 0)
|
||||||
fprintf(logfile, "%s: ! supervisor\n", __func__);
|
fprintf(logfile, "%s: ! supervisor\n", __func__);
|
||||||
RET_PRIVOPC(ctx);
|
RET_PRIVOPC(ctx);
|
||||||
return;
|
return;
|
||||||
|
@ -3434,7 +3434,7 @@ GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
|
||||||
RET_PRIVOPC(ctx);
|
RET_PRIVOPC(ctx);
|
||||||
#else
|
#else
|
||||||
if (unlikely(!ctx->supervisor)) {
|
if (unlikely(!ctx->supervisor)) {
|
||||||
if (loglevel)
|
if (loglevel != 0)
|
||||||
fprintf(logfile, "%s: ! supervisor\n", __func__);
|
fprintf(logfile, "%s: ! supervisor\n", __func__);
|
||||||
RET_PRIVOPC(ctx);
|
RET_PRIVOPC(ctx);
|
||||||
return;
|
return;
|
||||||
|
@ -5803,7 +5803,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
|
||||||
}
|
}
|
||||||
/* Is opcode *REALLY* valid ? */
|
/* Is opcode *REALLY* valid ? */
|
||||||
if (unlikely(handler->handler == &gen_invalid)) {
|
if (unlikely(handler->handler == &gen_invalid)) {
|
||||||
if (loglevel > 0) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "invalid/unsupported opcode: "
|
fprintf(logfile, "invalid/unsupported opcode: "
|
||||||
"%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
|
"%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
|
||||||
opc1(ctx.opcode), opc2(ctx.opcode),
|
opc1(ctx.opcode), opc2(ctx.opcode),
|
||||||
|
@ -5816,7 +5816,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
if (unlikely((ctx.opcode & handler->inval) != 0)) {
|
if (unlikely((ctx.opcode & handler->inval) != 0)) {
|
||||||
if (loglevel > 0) {
|
if (loglevel != 0) {
|
||||||
fprintf(logfile, "invalid bits: %08x for opcode: "
|
fprintf(logfile, "invalid bits: %08x for opcode: "
|
||||||
"%02x -%02x - %02x (%08x) 0x" ADDRX "\n",
|
"%02x -%02x - %02x (%08x) 0x" ADDRX "\n",
|
||||||
ctx.opcode & handler->inval, opc1(ctx.opcode),
|
ctx.opcode & handler->inval, opc1(ctx.opcode),
|
||||||
|
|
4
vl.h
4
vl.h
|
@ -1172,6 +1172,10 @@ int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
|
||||||
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
|
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
|
||||||
dcr_read_cb drc_read, dcr_write_cb dcr_write);
|
dcr_read_cb drc_read, dcr_write_cb dcr_write);
|
||||||
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
|
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
|
||||||
|
/* Embedded PowerPC reset */
|
||||||
|
void ppc40x_core_reset (CPUState *env);
|
||||||
|
void ppc40x_chip_reset (CPUState *env);
|
||||||
|
void ppc40x_system_reset (CPUState *env);
|
||||||
#endif
|
#endif
|
||||||
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
|
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue