hw/arm/armsse: Make SRAM bank size configurable
For the IoTKit the SRAM bank size is always 32K (15 bits); for the SSE-200 this is a configurable parameter, which defaults to 32K but can be changed when it is built into a particular SoC. For instance the Musca-B1 board sets it to 128K (17 bits). Make the bank size a QOM property. We follow the SSE-200 hardware in naming the parameter SRAM_ADDR_WIDTH, which specifies the number of address bits of a single SRAM bank. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-11-peter.maydell@linaro.org
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@ -221,6 +221,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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DeviceState *dev_apb_ppc1;
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DeviceState *dev_secctl;
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DeviceState *dev_splitter;
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uint32_t addr_width_max;
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if (!s->board_memory) {
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error_setg(errp, "memory property was not set");
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@ -232,6 +233,15 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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return;
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}
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/* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
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assert(is_power_of_2(info->sram_banks));
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addr_width_max = 24 - ctz32(info->sram_banks);
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if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) {
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error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d",
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addr_width_max);
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return;
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}
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/* Handling of which devices should be available only to secure
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* code is usually done differently for M profile than for A profile.
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* Instead of putting some devices only into the secure address space,
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@ -352,8 +362,10 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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for (i = 0; i < info->sram_banks; i++) {
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char *ramname = g_strdup_printf("armsse.sram%d", i);
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SysBusDevice *sbd_mpc;
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uint32_t sram_bank_size = 1 << s->sram_addr_width;
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memory_region_init_ram(&s->sram[i], NULL, ramname, 0x00008000, &err);
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memory_region_init_ram(&s->sram[i], NULL, ramname,
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sram_bank_size, &err);
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g_free(ramname);
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if (err) {
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error_propagate(errp, err);
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@ -372,7 +384,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
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}
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/* Map the upstream end of the MPC into the right place... */
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sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]);
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memory_region_add_subregion(&s->container, 0x20000000 + i * 0x8000,
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memory_region_add_subregion(&s->container,
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0x20000000 + i * sram_bank_size,
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sysbus_mmio_get_region(sbd_mpc, 1));
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/* ...and its register interface */
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memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000,
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@ -748,6 +761,7 @@ static Property armsse_properties[] = {
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MemoryRegion *),
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DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
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DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
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DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
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DEFINE_PROP_END_OF_LIST()
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};
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@ -146,6 +146,7 @@ typedef struct ARMSSE {
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MemoryRegion *board_memory;
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uint32_t exp_numirq;
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uint32_t mainclk_frq;
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uint32_t sram_addr_width;
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} ARMSSE;
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typedef struct ARMSSEInfo ARMSSEInfo;
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