target-ppc: convert ld64 to use new macro
Use macro for ld64 as well, this changes the function signature from gen_qemu_ld64 => gen_qemu_ld64_i64. Replace this at all the call sites. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
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09bfe50d57
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4f364fe76f
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@ -2488,12 +2488,7 @@ static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
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GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL))
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GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL))
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static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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{
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TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
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tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
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}
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GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
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static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
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{
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@ -2612,12 +2607,12 @@ GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
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/* lwax */
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GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
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/* ldux */
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GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
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GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B);
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/* ldx */
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GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
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GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B);
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/* CI load/store variants */
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GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
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GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
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GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
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GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
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GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
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@ -2640,7 +2635,7 @@ static void gen_ld(DisasContext *ctx)
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gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
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} else {
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/* ld - ldu */
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gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
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gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
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}
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if (Rc(ctx->opcode))
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tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
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@ -2677,16 +2672,16 @@ static void gen_lq(DisasContext *ctx)
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EA = tcg_temp_new();
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gen_addr_imm_index(ctx, EA, 0x0F);
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/* We only need to swap high and low halves. gen_qemu_ld64 does necessary
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64-bit byteswap already. */
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/* We only need to swap high and low halves. gen_qemu_ld64_i64 does
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necessary 64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
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gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
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gen_addr_add(ctx, EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
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gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
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} else {
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gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
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gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA);
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gen_addr_add(ctx, EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
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gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA);
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}
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tcg_temp_free(EA);
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}
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@ -3184,7 +3179,7 @@ STCX(stwcx_, 4);
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#if defined(TARGET_PPC64)
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/* ldarx */
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LARX(ldarx, 8, ld64);
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LARX(ldarx, 8, ld64_i64);
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/* lqarx */
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static void gen_lqarx(DisasContext *ctx)
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@ -3210,11 +3205,11 @@ static void gen_lqarx(DisasContext *ctx)
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gpr1 = cpu_gpr[rd];
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gpr2 = cpu_gpr[rd+1];
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}
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gen_qemu_ld64(ctx, gpr1, EA);
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gen_qemu_ld64_i64(ctx, gpr1, EA);
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tcg_gen_mov_tl(cpu_reserve, EA);
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gen_addr_add(ctx, EA, EA, 8);
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gen_qemu_ld64(ctx, gpr2, EA);
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gen_qemu_ld64_i64(ctx, gpr2, EA);
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tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
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tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
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@ -6601,12 +6596,12 @@ GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
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#if defined(TARGET_PPC64)
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GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
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GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
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GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
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GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
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GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B)
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GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B)
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GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
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/* HV/P7 and later only */
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GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
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GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST)
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GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
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GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
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GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
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@ -672,7 +672,7 @@ static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
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}
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/* lfd lfdu lfdux lfdx */
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GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
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GEN_LDFS(lfd, ld64_i64, 0x12, PPC_FLOAT);
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/* lfs lfsu lfsux lfsx */
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GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
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@ -687,16 +687,16 @@ static void gen_lfdp(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_FLOAT);
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EA = tcg_temp_new();
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gen_addr_imm_index(ctx, EA, 0);
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/* We only need to swap high and low halves. gen_qemu_ld64 does necessary
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64-bit byteswap already. */
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/* We only need to swap high and low halves. gen_qemu_ld64_i64 does
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necessary 64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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} else {
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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}
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tcg_temp_free(EA);
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}
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@ -712,16 +712,16 @@ static void gen_lfdpx(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_FLOAT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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/* We only need to swap high and low halves. gen_qemu_ld64 does necessary
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64-bit byteswap already. */
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/* We only need to swap high and low halves. gen_qemu_ld64_i64 does
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necessary 64-bit byteswap already. */
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if (unlikely(ctx->le_mode)) {
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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} else {
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
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}
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tcg_temp_free(EA);
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}
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@ -924,9 +924,9 @@ static void gen_lfq(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_FLOAT);
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t0 = tcg_temp_new();
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gen_addr_imm_index(ctx, t0, 0);
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gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0);
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gen_addr_add(ctx, t0, t0, 8);
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gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
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gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0);
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tcg_temp_free(t0);
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}
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@ -940,9 +940,9 @@ static void gen_lfqu(DisasContext *ctx)
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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gen_addr_imm_index(ctx, t0, 0);
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gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0);
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gen_addr_add(ctx, t1, t0, 8);
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gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
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gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1);
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if (ra != 0)
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tcg_gen_mov_tl(cpu_gpr[ra], t0);
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tcg_temp_free(t0);
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@ -958,10 +958,10 @@ static void gen_lfqux(DisasContext *ctx)
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TCGv t0, t1;
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t0 = tcg_temp_new();
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gen_addr_reg_index(ctx, t0);
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gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0);
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t1 = tcg_temp_new();
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gen_addr_add(ctx, t1, t0, 8);
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gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
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gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t1);
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tcg_temp_free(t1);
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if (ra != 0)
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tcg_gen_mov_tl(cpu_gpr[ra], t0);
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@ -976,9 +976,9 @@ static void gen_lfqx(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_FLOAT);
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t0 = tcg_temp_new();
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gen_addr_reg_index(ctx, t0);
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gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
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gen_qemu_ld64_i64(ctx, cpu_fpr[rd], t0);
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gen_addr_add(ctx, t0, t0, 8);
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gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
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gen_qemu_ld64_i64(ctx, cpu_fpr[(rd + 1) % 32], t0);
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tcg_temp_free(t0);
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}
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@ -617,7 +617,7 @@ static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
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static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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gen_qemu_ld64(ctx, t0, addr);
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gen_qemu_ld64_i64(ctx, t0, addr);
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gen_store_gpr64(rD(ctx->opcode), t0);
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tcg_temp_free_i64(t0);
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}
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@ -26,16 +26,16 @@ static void glue(gen_, name)(DisasContext *ctx)
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EA = tcg_temp_new(); \
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gen_addr_reg_index(ctx, EA); \
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tcg_gen_andi_tl(EA, EA, ~0xf); \
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/* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
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64-bit byteswap already. */ \
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/* We only need to swap high and low halves. gen_qemu_ld64_i64 does \
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necessary 64-bit byteswap already. */ \
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if (ctx->le_mode) { \
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gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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} else { \
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gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
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tcg_gen_addi_tl(EA, EA, 8); \
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gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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gen_qemu_ld64_i64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
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} \
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tcg_temp_free(EA); \
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}
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@ -34,7 +34,7 @@ static void gen_##name(DisasContext *ctx) \
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tcg_temp_free(EA); \
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}
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VSX_LOAD_SCALAR(lxsdx, ld64)
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VSX_LOAD_SCALAR(lxsdx, ld64_i64)
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VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
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VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
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VSX_LOAD_SCALAR(lxsspx, ld32fs)
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@ -49,9 +49,9 @@ static void gen_lxvd2x(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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gen_qemu_ld64_i64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
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gen_qemu_ld64_i64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
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tcg_temp_free(EA);
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}
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@ -65,7 +65,7 @@ static void gen_lxvdsx(DisasContext *ctx)
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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gen_qemu_ld64_i64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
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tcg_temp_free(EA);
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}
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