aspeed/timer: Status register contains reload for stopped timer
From the datasheet: This register stores the current status of counter #N. When timer enable bit TMC30[N * b] is disabled, the reload register will be loaded into this counter. When timer bit TMC30[N * b] is set, the counter will start to decrement. CPU can update this register value when enable bit is set. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190618165311.27066-9-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -187,7 +187,11 @@ static uint64_t aspeed_timer_get_value(AspeedTimer *t, int reg)
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switch (reg) {
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switch (reg) {
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case TIMER_REG_STATUS:
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case TIMER_REG_STATUS:
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value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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if (timer_enabled(t)) {
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value = calculate_ticks(t, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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} else {
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value = t->reload;
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}
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break;
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break;
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case TIMER_REG_RELOAD:
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case TIMER_REG_RELOAD:
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value = t->reload;
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value = t->reload;
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