target/ppc: Use MMUAccessType in mmu-hash64.c
We must leave the 'int rwx' parameter to ppc_hash64_handle_mmu_fault for now, but will clean that up later. Signed-off-by: Ricgard Henderson <richard.henderson@linaro.org> Message-Id: <20210518201146.794854-4-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -877,10 +877,12 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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hwaddr ptex;
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ppc_hash_pte64_t pte;
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int exec_prot, pp_prot, amr_prot, prot;
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MMUAccessType access_type;
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int need_prot;
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hwaddr raddr;
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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access_type = rwx;
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/*
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* Note on LPCR usage: 970 uses HID4, but our special variant of
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@ -891,7 +893,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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*/
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/* 1. Handle real mode accesses */
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if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
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if (access_type == MMU_INST_FETCH ? !msr_ir : !msr_dr) {
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/*
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* Translation is supposedly "off", but in real mode the top 4
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* effective address bits are (mostly) ignored
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@ -924,14 +926,19 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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/* Emulated old-style RMO mode, bounds check against RMLS */
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if (raddr >= limit) {
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if (rwx == 2) {
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, SRR1_PROTFAULT);
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} else {
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int dsisr = DSISR_PROTFAULT;
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if (rwx == 1) {
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dsisr |= DSISR_ISSTORE;
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}
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ppc_hash64_set_dsi(cs, eaddr, dsisr);
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break;
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case MMU_DATA_LOAD:
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ppc_hash64_set_dsi(cs, eaddr, DSISR_PROTFAULT);
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break;
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case MMU_DATA_STORE:
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ppc_hash64_set_dsi(cs, eaddr,
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DSISR_PROTFAULT | DSISR_ISSTORE);
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break;
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default:
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g_assert_not_reached();
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}
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return 1;
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}
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@ -954,13 +961,19 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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exit(1);
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}
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/* Segment still not found, generate the appropriate interrupt */
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if (rwx == 2) {
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switch (access_type) {
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case MMU_INST_FETCH:
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cs->exception_index = POWERPC_EXCP_ISEG;
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env->error_code = 0;
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} else {
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break;
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case MMU_DATA_LOAD:
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case MMU_DATA_STORE:
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cs->exception_index = POWERPC_EXCP_DSEG;
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env->error_code = 0;
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env->spr[SPR_DAR] = eaddr;
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break;
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default:
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g_assert_not_reached();
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}
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return 1;
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}
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@ -968,7 +981,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
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skip_slb_search:
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/* 3. Check for segment level no-execute violation */
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if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
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if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) {
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ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD);
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return 1;
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}
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@ -976,14 +989,18 @@ skip_slb_search:
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/* 4. Locate the PTE in the hash table */
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ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift);
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if (ptex == -1) {
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if (rwx == 2) {
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switch (access_type) {
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case MMU_INST_FETCH:
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ppc_hash64_set_isi(cs, SRR1_NOPTE);
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} else {
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int dsisr = DSISR_NOPTE;
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if (rwx == 1) {
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dsisr |= DSISR_ISSTORE;
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}
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ppc_hash64_set_dsi(cs, eaddr, dsisr);
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break;
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case MMU_DATA_LOAD:
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ppc_hash64_set_dsi(cs, eaddr, DSISR_NOPTE);
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break;
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case MMU_DATA_STORE:
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ppc_hash64_set_dsi(cs, eaddr, DSISR_NOPTE | DSISR_ISSTORE);
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break;
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default:
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g_assert_not_reached();
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}
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return 1;
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}
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@ -997,11 +1014,11 @@ skip_slb_search:
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amr_prot = ppc_hash64_amr_prot(cpu, pte);
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prot = exec_prot & pp_prot & amr_prot;
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need_prot = prot_for_access_type(rwx);
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need_prot = prot_for_access_type(access_type);
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if (need_prot & ~prot) {
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/* Access right violation */
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qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
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if (rwx == 2) {
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if (access_type == MMU_INST_FETCH) {
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int srr1 = 0;
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if (PAGE_EXEC & ~exec_prot) {
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srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */
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@ -1017,7 +1034,7 @@ skip_slb_search:
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if (need_prot & ~pp_prot) {
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dsisr |= DSISR_PROTFAULT;
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}
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if (rwx == 1) {
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if (access_type == MMU_DATA_STORE) {
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dsisr |= DSISR_ISSTORE;
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}
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if (need_prot & ~amr_prot) {
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@ -1036,7 +1053,7 @@ skip_slb_search:
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ppc_hash64_set_r(cpu, ptex, pte.pte1);
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}
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if (!(pte.pte1 & HPTE64_R_C)) {
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if (rwx == 1) {
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if (access_type == MMU_DATA_STORE) {
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ppc_hash64_set_c(cpu, ptex, pte.pte1);
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} else {
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/*
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