target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state
Hoist the variable load for PSTATE into the existing test vs is_a64. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -11197,7 +11197,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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ARMMMUIdx mmu_idx = arm_mmu_idx(env);
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int current_el = arm_current_el(env);
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int fp_el = fp_exception_el(env, current_el);
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uint32_t flags;
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uint32_t flags, pstate_for_ss;
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if (is_a64(env)) {
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*pc = env->pc;
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@ -11205,6 +11205,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
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flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
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}
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pstate_for_ss = env->pstate;
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} else {
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*pc = env->regs[15];
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@ -11257,9 +11258,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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|| arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) {
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flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
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}
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pstate_for_ss = env->uncached_cpsr;
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}
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/* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
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/*
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* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
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* states defined in the ARM ARM for software singlestep:
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* SS_ACTIVE PSTATE.SS State
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* 0 x Inactive (the TB flag for SS is always 0)
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@ -11267,16 +11270,9 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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* 1 1 Active-not-pending
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* SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
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*/
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if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE)) {
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if (is_a64(env)) {
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if (env->pstate & PSTATE_SS) {
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flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
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}
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} else {
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if (env->uncached_cpsr & PSTATE_SS) {
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flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
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}
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}
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if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
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(pstate_for_ss & PSTATE_SS)) {
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flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
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}
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*pflags = flags;
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