target/mips: Add bit definitions for DSP R3 ASE
Add DSP R3 ASE related bit definition for insn_flags and hflags. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
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@ -795,6 +795,7 @@ struct CPUMIPSState {
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/* MIPS DSP resources access. */
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#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
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#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
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#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
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/* Extra flag about HWREna register. */
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#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
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#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
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@ -53,6 +53,7 @@
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#define ASE_MDMX 0x0000000400000000ULL
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#define ASE_DSP 0x0000000800000000ULL
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#define ASE_DSPR2 0x0000001000000000ULL
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#define ASE_DSPR3 0x0000002000000000ULL
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#define ASE_MT 0x0000004000000000ULL
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#define ASE_SMARTMIPS 0x0000008000000000ULL
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#define ASE_MICROMIPS 0x0000010000000000ULL
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